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NCP382LD05AA-R2G 데이터시트(PDF) 8 Page - ON Semiconductor

부품명 NCP382LD05AA-R2G
상세설명  Fixed Current-Limiting Power-Distribution Switches
PDF  12 Pages
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제조업체  ONSEMI [ON Semiconductor]
홈페이지  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NCP382LD05AA-R2G 데이터시트(HTML) 8 Page - ON Semiconductor

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NCP382
http://onsemi.com
8
Enable Input
Enable pin must be driven by a logic signal (CMOS or
TTL compatible) or connected to the GND or VIN. A logic
low on ENX or high on ENX turns−on the device. A logic
high on ENX or low on ENX turns off device and reduces
the current consumption down to IINOFF.
Blocking Control
The blocking control circuitry switches the bulk of the
power MOS. When the part is off, the body diode limits the
leakage current IREV from OUTX to IN. In this mode, anode
of the body diode is connected to IN pin and cathode is
connected to OUTX pin. In operating condition, anode of
the body diode is connected to OUTX pin and cathode is
connected to IN pin preventing the discharge of the power
supply.
APPLICATION INFORMATION
Power Dissipation
The junction temperature of the device depends on
different contributing factors such as board layout, ambient
temperature, device environment, etc... Yet, the main
contributor in term of junction temperature is the power
dissipation of the power MOSFET. Assuming this, the
power dissipation and the junction temperature in normal
mode can be calculated with the following equations:
PD + RDS(on)
IOUT1
2
) IOUT2
2
(eq. 2)
PD
= Power dissipation (W)
RDS(on)
= Power MOSFET on resistance (
W)
IOUTx
= Output current in channel X (A)
TJ + PD RqJA ) TA
(eq. 3)
TJ
= Junction temperature (
°C)
RqJA
= Package thermal resistance (
°C/W)
TA
= Ambient temperature (
°C)
Power dissipation in regulation mode can be calculated by
taking into account the drop VIN −VOUTX link to the load by
the following relation:
PD + VIN * RLOAD1 IOCP ) VIN * RLOAD2 IOCP
(eq. 4)
IOCP
PD
= Power dissipation (W)
VIN
= Input Voltage (V)
RLOADX
= Load Resistance on channel X (
W)
IOCP
= Output regulated current (A)
PCB Recommendations
The NCP382 integrates two PMOS FET rated up to 2 A,
and the PCB design rules must be respected to properly
evacuate the heat out of the silicon. The DFN8 PAD1 must
be connected to ground plane to increase the heat transfer if
necessary. Of course, in any case, this pad must not connect
to any other potential. By increasing PCB area, the RqJA of
the package can be decreased, allowing higher current
.



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