LP2996

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LP2996

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LP2996-N

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SNOSA40J – NOVEMBER 2002 – REVISED MARCH 2013

DDR-II APPLICATIONS

With the separate VDDQ pin and an internal resistor divider it is possible to use the LP2996-N in applications

utilizing DDR-II memory. Figure 25 and Figure 26 show several implementations of recommended circuits with

output curves displayed in the Typical Performance Characteristics. Figure 25 shows the recommended circuit

configuration for DDR-II applications. The output stage is connected to the 1.8V rail and the AVIN pin can be

connected to either a 3.3V or 5V rail. For new designs, the LP2997 or LP2998 is recommended for DDR-II

applications.

Figure 27. Recommended DDR-II Termination

If it is not desirable to use the 1.8V rail it is possible to connect the output stage to a 3.3V rail. Care should be

output voltages. For this reason it is not recommended to power PVIN off a rail higher than the nominal 3.3V.

The advantage of this configuration is that it has the ability to source and sink a higher maximum continuous

current.

Figure 28. DDR-II Termination with higher voltage rails

LEVEL SHIFTING

If standards other than SSTL-2 are required, such as SSTL-3, it may be necessary to use a different scaling

pin. This has been illustrated in Figure 29 and Figure 30. Figure 29 shows how to use two resistors to level shift

can be used.

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