IN1

IN2

MUX

T/H

SCLK

GND

CS

DIN

DOUT

CONTROL

LOGIC

10-BIT

SUCCESSIVE

APPROXIMATION

ADC

GND

ADC102S021

SNAS281G – FEBRUARY 2005 – REVISED MARCH 2013

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Block Diagram

Figure 2.

Table 2. Pin Descriptions and Equivalent Circuits

Pin No.

Name

Description

ANALOG I/O

5,4

IN1 and IN2

DIGITAL I/O

8

SCLK

Digital clock input. This clock directly controls the conversion and readout processes.

7

DOUT

Digital data output. The output samples are clocked out of this pin on falling edges of the SCLK pin.

Digital data input. The ADC102S021's Control Register is loaded through this pin on rising edges of

6

DIN

the SCLK pin.

Chip select. On the falling edge of CS, a conversion process begins. Conversions continue as long

1

CS

as CS is held low.

POWER SUPPLY

Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and bypassed to

2

GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within 1 cm of the power pin.

3

GND

The ground return for the die.

2

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