CD54HC4017

DECADE COUNTER/DIVIDER

WITH TEN DECODED OUTPUTS

SGDS011 – MAY 1999

1

POST OFFICE BOX 655303

Times

Also Available in Chip Form (H)

description

The CD54HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each

decoded output normally is low and sequentially goes high on the low-to-high transition of the clock (CP) input.

Each output stays high for one clock period of the ten-clock-period cycle. The terminal count (TC) output

transitions low to high after output ten (9) goes low, and can be used in conjunction with the clock enable (CE)

input to cascade several stages. CE disables counting when in the high state. The master reset (MR) input, when

taken high, sets all the decoded outputs, except 0, to low.

The CD54HC4017 is characterized for operation over the full military temperature range of –55

°C to 125°C.

FUNCTION TABLE

INPUTS

OUTPUT STATE†

CP

CE

MR

OUTPUT STATE†

L

X

L

No change

X

H

L

No change

X

XH

0 = H

1–9 = L

↑

L

L

Increments counter

↓

X

L

No change

X

↑

L

No change

H

↓

L

Increments counter

† If n < 5, TC = H; otherwise, TC = L.

Copyright

© 1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

5

1

0

2

6

7

3

GND

MR

CP

CE

TC

9

4

8

F PACKAGE

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