| 전자부품 데이터시트 검색엔진 |
|
CDC351DBLE 데이터시트(PDF) 5 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
CDC351DBLE 데이터시트(HTML) 5 Page - Texas Instruments |
|
5 / 13 page ![]() www.ti.com th tsu From Output Under Test CL = 50 pF (see Note A) LOAD CIRCUIT S1 6 V Open GND 500 Ω 500 Ω TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 6 V GND Output Control (low-level enabling) Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) VOL VOH tPZL tPZH tPLZ tPHZ 1.5 V 1.5 V 3 V 0 V 1.5 V VOL + 0.3 V 1.5 V VOH - 0.3 V ≈ 0 V 3 V Data Input Timing Input 1.5 V 3 V 0 V 1.5 V 1.5 V 3 V 0 V 3 V 0 V 1.5 V 1.5 V tw Input VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS tPLH tPHL Output 1.5 V 1.5 V 3 V 0 V 1.5 V VOH VOL Input 0.8 V 2 V tr tf 0.8 V 2 V CDC351. CDC351I 1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS441D – FEBRUARY 1994 – REVISED OCTOBER 2003 A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 Ω, tr≤ 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 5 |
|
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |