CLC006

8

4

3

1

5

2

R7

75:

C2

0.1 PF

R6

75:

C1

0.1 PF

J3

VR1

10k

6

7

J4

J2

R1

154:

R4

75:

R3

154:

R5

75:

J1

-

+

1 k:

1 k:

3.15 k:

3.4 k:

4

3

0.5 mA

CLC006

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SNLS015G – AUGUST 1998 – REVISED APRIL 2013

OUTPUT AMPLITUDE ADJUSTMENT

The high and low output levels of the CLC006 are set by a circuit shown simplified in Figure 10. Output high and

4) and the power supplies. The resistor networks affect the high and low output levels by changing the internally

determine output voltage levels have accurate ratios, their absolute values may be controlled only within about

±15% of nominal. Even so, without external adjustment, output voltages are well controlled. A final design should

accommodate the variation in externally set output voltages due to the CLC006’s part-to-part and external

component tolerances.

Output voltage swing may be reduced with the circuit shown in Figure 11. A single resistance chosen with the aid

of the graph, Figure 12, is connected between pins 3 and 4. Output voltage swing may be increased with the

circuit of Figure 13. Figure 14 is used to estimate a value for resistor R. Note that both of these circuits and the

accompanying graphs assume that the CLC006 is loaded with the standard 150

Ω. Be aware that output loading

will affect the output swing and the high and low levels. It may be necessary to empirically select resistances

used to set output levels when the D.C. loading on the CLC006 differs appreciably from 150

Ω.

Figure 10. Equivalent Bias Generation Circuit

Figure 11. Differential Input Reduced Output

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