AD9852ASQZ datasheet(22/52 Pages) AD

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AD9852

Rev. E | Page 22 of 52

Additional flexibility in the ramped FSK mode is provided by

the AD9852’s ability to respond to changes in the 48-bit delta

frequency word and/or the 20-bit ramp rate counter at any time

during the ramping from F1 to F2 or vice versa. To create these

nonlinear frequency changes, it is necessary to combine several

linear ramps with different slopes in a piecewise fashion. This is

done by programming and executing a linear ramp at a rate or

slope and then altering the slope (by changing the ramp rate

clock or delta frequency word, or both). Changes in slope can

be made as often as needed before the destination frequency has

been reached to form the desired nonlinear frequency sweep

response. These piecewise changes can be precisely timed using

the 32-bit internal update clock (see the Internal and External

Update Clock section).

Nonlinear ramped FSK has the appearance of the chirp function

shown in Figure 41. The major difference between a ramped

FSK function and a chirp function is that FSK is limited to

operation between F1 and F2, whereas chirp operation has no

F2 limit frequency.

Two additional control bits (CLR ACC1 and CLR ACC2) are

available in the ramped FSK mode that allow more options. Setting

CLR ACC1 (Register Address 1F hex) high clears the 48-bit

frequency accumulator (ACC1) output with a retriggerable

one-shot pulse of one system clock duration. If the CLR ACC1

bit is left high, a one-shot pulse is delivered on the rising edge of

every update clock. The effect is to interrupt the current ramp,

reset the frequency to the start point (F1 or F2), and then

continue to ramp up (or down) at the previous rate. This occurs

even when a static F1 or F2 destination frequency has been

achieved.

Alternatively, the CLR ACC2 control bit (Register Address 1F hex)

can be used to clear both the frequency accumulator (ACC1)

and the phase accumulator (ACC2). When this bit is set high,

the output of the phase accumulator results in 0 Hz output from

the DDS. As long as this bit is set high, the frequency and phase

accumulators are cleared, resulting in 0 Hz output. To return to

previous DDS operation, CLR ACC2 must be set to logic low.

CHIRP (MODE 011)

Chirp mode is also known as pulsed FM. Most chirp systems

use a linear FM sweep pattern, but the AD9852 can also support

nonlinear patterns. In radar applications, use of chirp or pulsed

FM allows operators to significantly reduce the output power

needed to achieve the same result a single frequency radar

system produces. Figure 41 represents a very low resolution

nonlinear chirp that demonstrates the different slopes created

by varying the time steps (ramp rate) and frequency steps (delta

frequency word).

The AD9852 permits precise, internally generated linear,

or externally programmed nonlinear, pulsed or continuous

FM over the complete frequency range, duration, frequency

resolution, and sweep direction(s). All of these options are user

programmable. A block diagram of the FM chirp components

is shown in Figure 40.

FREQUENCY

MODE

TW1

TW2

FSK DATA

000 (DEFAULT)

010 (RAMPED FSK)

I/O UD CLK

Figure 39. Effect of Premature Ramped FSK Data

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