REV. C

–2–

AD9884A–SPECIFICATIONS

Clock Frequency = Maximum, Control Registers Programmed to Default State)

Test

AD9884AKS-100

AD9884AKS-140

Parameter

Temp

Level

Min

Typ

Max

Min

Typ

Max

Unit

RESOLUTION

8

8

Bits

DC ACCURACY

Differential Nonlinearity

25

°CI

±0.5

±1.0

±0.5

+1.15/–1.0

LSB

Full

VI

±1.0

+1.25/–1.0

LSB

Integral Nonlinearity

25

°CI

±0.5

±1.25

±0.8

±1.4

LSB

Full

VI

±1.75

±2.5

LSB

No Missing Codes

Full

VI

Guaranteed

Guaranteed

ANALOG INPUT

Input Voltage Range

Minimum

Full

VI

0.5

0.5

V p-p

Maximum

Full

VI

1.0

1.0

V p-p

Gain Tempco

25

°C

V

100

280

ppm/

°C

Input Bias Current

25

°CI

1

1

µA

Full

VI

1

1

µA

Input Offset Voltage

Full

VI

7

50

7

50

mV

Input Full-Scale Matching

Full

VI

1.5

5.0

1.5

5.0

%FS

Offset Adjustment Range

Full

VI

22

23.5

25

22

23.5

25

%FS

REFERENCE OUTPUT

Output Voltage

Full

VI

1.20

1.25

1.30

1.20

1.25

1.30

V

Temperature Coefficient

Full

V

±50

±50

ppm/

°C

SWITCHING PERFORMANCE

Maximum Conversion Rate

Full

VI

100

140

MSPS

Minimum Conversion Rate

Full

IV

10

10

MSPS

Full

IV

–0.5

+2.0

–0.5

+2.0

ns

Full

VI

4.7

4.7

µs

Full

VI

4.0

4.0

µs

Full

VI

0

0

µs

Full

VI

4.7

4.7

µs

Full

VI

4.0

4.0

µs

Full

VI

250

250

ns

Full

VI

4.7

4.7

µs

Full

VI

4.0

4.0

µs

HSYNC Input Frequency

Full

IV

15

110

15

110

kHz

Maximum PLL Clock Rate

Full

VI

100

140

MHz

Minimum PLL Clock Rate

Full

IV

20

20

MHz

PLL Jitter

25

°C

IV

400

700

1

475

750

2

ps p-p

Full

IV

1000

1

1000

2

ps p-p

Sampling Phase Tempco

Full

IV

15

15

ps/

°C

DIGITAL INPUTS

Full

VI

2.5

2.5

V

Full

VI

0.8

0.8

V

Full

VI

–1.0

–1.0

µA

Full

VI

+1.0

+1.0

µA

Input Capacitance

25

°CV

3

3

pF

DIGITAL OUTPUTS

Full

VI

V

Full

VI

0.1

0.1

V

Duty Cycle

DATACK, DATACK

Full

IV

45

50

55

45

50

55

%

Output Coding

Binary

Binary