ADN2891

Rev. A | Page 6 of 16

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

5

6

7

8

16

15

14

13

TOP VIEW

(Not to Scale)

DRVCC

12

OUTN

10

DRVEE

9

OUTP

11

ADN2891

Figure 2. Pin Configuration

Note that the LFCSP has an exposed pad on the bottom. To improve heat dissipation, the exposed pad must be soldered to the GND plane

with filled vias.

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

I/O Type

Descriptions

1

1

AVCC

P

Analog Power Supply.

2

PIN

AI

Differential Data Input, Positive Port, 50 Ω On-Chip Termination.

3

NIN

AI

Differential Data Input, Negative Port, 50 Ω On-Chip Termination.

4

AVEE

P

Analog Ground.

5

THRADJ

AO

LOS Threshold Adjust Resistor.

6

CAZ1

AI

If needed, one capacitor can connect between the CAZ1 and CAZ2 pin for

input offset correction.

7

CAZ2

AI

If needed, one capacitor can connect between the CAZ1 and CAZ2 pin for

input offset correction.

8

LOS

DO

LOS Detector Output, Open Collector.

9

DRVEE

P

Output Buffer Ground.

10

OUTN

DO

Differential Data Output, CML, Negative Port, 50 Ω On-Chip Termination.

11

OUTP

DO

Differential Data Output, CML, Positive Port, 50 Ω On-Chip Termination.

12

DRVCC

P

Output Buffer Power Supply.

13

SQUELCH

DI

Disable Outputs, 100 kΩ On-Chip Pull-Down Resistor.

14

RSSI_OUT

AO

Average Current Output.

15

PD_VCC

P

Power Input for RSSI Measurement.

16

PD_CATHODE

AO

Photodiode Bias Voltage.

Pad

P

Connect to Ground.

Exposed

Pad