REV. D

AD8072/AD8073

–10–

Crosstalk

Crosstalk between internal amplifiers may vary depending on

which amplifier is being driven and how many amplifiers are

being driven. This variation typically stems from pin location on

the package and the internal layout of the IC itself. Table I

illustrates the typical crosstalk results for a combination of

conditions.

Table I. AD8073JR Crosstalk Table (dB)

Receive Amplifier

AD8073JR

12

3

1

X

–60

–56

Drive

2

–60

X

–60

Amplifier

3

–54

–60

X

All Hostile

–53

–55

–54

CONDITIONS

±5 V

Ω, R

Ω

Layout Considerations

The specified high speed performance of the AD8072 and

AD8073 require careful attention to board layout and compo-

nent selection. Proper RF design techniques and low parasitic

component selection are mandatory.

The PCB should have a ground plane covering all unused portions

of the component side of the board to provide a low impedance

ground path. The ground plane should be removed from the

area near the input pins to reduce stray capacitance.

Chip capacitors should be used for supply bypassing. One end

of the capacitor should be connected to the ground plane and

the other within 1/8 inches of each power pin. An additional

large (4.7

µF–10 µF) tantalum electrolytic capacitor should be

connected in parallel, but not necessarily as close to the supply

pins, to provide current for fast large-signal changes at the

device’s output.

The feedback resistor should be located close to the inverting

input pin in order to keep the stray capacitance at this node to a

minimum. Capacitance variations of less than 1 pF at the invert-

ing input will affect high speed performance.

Stripline design techniques should be used for long signal traces

(greater than approximately 1 inch). These should be designed

with a characteristic impedance of 50

Ω or 75 Ω and be properly

terminated at each end.