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LTC1293BCSW 데이터시트(PDF) 3 Page - Linear Technology

부품명 LTC1293BCSW
상세설명  Single Chip 12-Bit Data Acquisition System
PDF  28 Pages
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제조업체  LINER [Linear Technology]
홈페이지  http://www.linear.com
Logo LINER - Linear Technology

LTC1293BCSW 데이터시트(HTML) 3 Page - Linear Technology

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LTC1293/LTC1294/LTC1296
129346fs
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Offset Error
(Note 4)
●
±3.0
±3.0
±3.0
LSB
Linearity Error (INL)
(Notes 4, 5)
●
±0.5
±0.5
±0.75
LSB
Gain Error
(Note 4)
●
±0.5
±1.0
±4.0
LSB
Minimum Resolution for which No
●
12
12
12
Bits
Missing Codes are Guaranteed
Analog and REF Input Range
(Note 7)
(V
–)–0.05V to VCC + 0.05V
V
On Channel Leakage Current (Note 8)
On Channel = 5V
●
±1
±1
±1
µA
Off Channel = 0V
On Channel = 0V
●
±1
±1
±1
µA
Off Channel = 5V
Off Channel Lekage Current (Note 8)
On Channel = 5V
●
±1
±1
±1
µA
Off Channel = 0V
On Channel = 0V
●
±1
±1
±1
µA
Off Channel = 5V
(Note 3)
LTC1293/4/6C
LTC1293/4/6D
LTC1293/4/6B
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fCLK
Clock Frequency
VCC = 5V (Note 6)
0.1
1.0
MHz
tSMPL
Analog Input Sample Time
See Operating Sequence
2.5
CLK Cycles
tCONV
Conversion Time
See Operating Sequence
12
CLK Cycles
tCYC
Total Cycle Time
See Operating Sequence (Note 6)
21 CLK
Cycles
+500ns
tdDO
Delay Time, CLK
↓ to DOUT Data Valid
See Test Circuits
●
160
300
ns
tdis
Delay Time, CS
↑ to DOUT Hi-Z
See Test Circuits
●
80
150
ns
ten
Delay Time, CLK
↓ to DOUT Enabled
See Test Circuits
●
80
200
ns
thDI
Hold Time, DIN after CLK↑
VCC = 5V (Note 6)
50
ns
thDO
Time Output Data Remains Valid After CLK
↓
130
ns
tf
DOUT Fall Time
See Test Circuits
●
65
130
ns
tr
DOUT Rise Time
See Test Circuits
●
25
50
ns
tWHCLK
CLK High Time
VCC = 5V (Note 6)
300
ns
tWLCLK
CLK Low Time
VCC = 5V (Note 6)
400
ns
tsuDI
Set-up Time, DIN Stable Before CLK↑
VCC = 5V (Note 6)
50
ns
tsuCS
Set-up Time, CS
↓ before CLK↑
VCC = 5V (Note 6)
50
ns
twHCS
CS High Time During Conversion
VCC = 5V (Note 6)
500
ns
twLCS
CS Low Time During Data Transfer
VCC = 5V (Note 6)
21
CLK Cycles
tenSSO
Delay Time, CLK
↓ to SSO↓
See Test Circuits
●
750
1500
ns
tdisSSO
Delay Time, CS
↓ to SSO↑
See Test Circuits
●
250
500
ns
CIN
Input Capacitance
Analog Inputs On Channel
100
pF
Analog Inputs Off Channel
5
Digital Inputs
5
LTC1293/4/6B
LTC1293/4/6C
LTC1293/4/6D
AC CHARACTERISTICS (Note 3)
CO VERTER A D
ULTIPLEXER CHARACTERISTICS



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