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LTC4061 데이터시트(PDF) 18 Page - Linear Technology |
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LTC4061 데이터시트(HTML) 18 Page - Linear Technology |
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18 / 20 page ![]() LTC4061 4061fd package DescripTion MOSFET, MP1, is used to prevent back conducting into the USB port when a wall adapter is present and a Schottky diode, D1, is used to prevent USB power loss through the 1k Ω pull-down resistor. Typically a wall adapter can supply more current than the 500mA limited USB port. Therefore, an N-channel MOSFET, MN1, and an extra 3.3k Ω program resistor are used to increase the charge current to 800mA when the wall adapter is present. + VCC D1 PROG IDET 3.3k 2k MN1 5V WALL ADAPTER ICHG = 800mA USB POWER ICHG = 500mA MP1 4061 F08 BAT LTC4061 1.25k Li-Ion BATTERY SYSTEM LOAD 1k C/5 Figure8.CombiningWallAdapterandUSBPower 3.00 0.10 (4 SIDES) NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.40 0.10 BOTTOM VIEW—EXPOSED PAD 1.65 0.10 (2 SIDES) 0.75 0.05 R = 0.125 TYP 2.38 0.10 (2 SIDES) 1 5 10 6 PIN 1 TOP MARK (SEE NOTE 6) 0.200 REF 0.00 – 0.05 (DD) DFN REV C 0310 0.25 0.05 2.38 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 1.65 0.05 (2 SIDES) 2.15 0.05 0.50 BSC 0.70 0.05 3.55 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC PIN 1 NOTCH R = 0.20 OR 0.35 45 CHAMFER DDPackage 10-LeadPlasticDFN(3mm ×3mm) (Reference LTC DWG # 05-08-1699 Rev C) |
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