AM3703CUS datasheet(222/280 Pages) TI

222 / 280 page

AM3715, AM3703

SPRS616F

– JUNE 2010 – REVISED AUGUST 2011

www.ti.com

Table 6-72. McBSP3 (Set #3) Timing Requirements

—T Multipoint Mode(4) (continued)

NO.

PARAMETER

OPP100

OPP50

UNIT

MIN

MAX

MIN

MAX

tw(clkxH)

Pulse duration, input clock mcbsp3_clkx high

0.5P(1)

tw(clkxL)

Pulse duration, input clock mcbsp3_clkx low

0.5P(1)

tdc(clkx)

Duty cycle error, input clock mcbsp3_clkx

–8.14

8.14

–8.14

8.14

B3(3)

tsu(drV-clkxAE)

Setup time, input data mcbsp3_dr valid before input

clock mcbsp3_clkx active edge

B4(3)

th(clkxAE-drV)

Hold time, input data mcbsp3_dr valid after input clock

2.4

mcbsp3_clkx active edge

B5(3)

tsu(fsxV-clkxAE)

Setup time, input frame synchronization mcbsp3_fsx

valid before input clock mcbsp3_clkx active edge

B6(3)

th(clkxAE-fsxV)

Hold time, input frame synchronization mcbsp3_fsx

2.4

valid after input clock mcbsp3_clkx active edge

(1) P = input clock mcbsp3_clkx period in ns

(2) For McBSP3, these timings concern only Set #3 (multiplexing mode in McBSP1 pins).

(3) See Section 6.6.1.1 for corresponding figures.

(4) See Section 4.3.4, Processor Clocks.

Table 6-73. McBSP3 (Set #3) Switching Characteristics

—T Multipoint Mode(1)

NO.

PARAMETER

OPP100

OPP50

UNIT

MIN

MAX

MIN

MAX

B8(2)

td(clkxAE-dxV)

Delay time, mcbsp3_clkx active edge to output data

0.6

15.89

0.6

28.68

mcbsp3_dx valid

(1) For McBSP3, these timings concern only Set #3 (multiplexing mode in McBSP1 pins).

(2) See Section 6.6.1.1 for corresponding figures.

222

Timing Requirements and Switching Characteristics

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