전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

ADuC7023BCBZ62I-R7 데이터시트(PDF) 79 Page - Analog Devices

부품명 ADuC7023BCBZ62I-R7
상세설명  Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU with Enhanced IRQ Handler
PDF  96 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

ADuC7023BCBZ62I-R7 데이터시트(HTML) 79 Page - Analog Devices

Back Button ADuC7023BCBZ62I-R7 Datasheet HTML 75Page - Analog Devices ADuC7023BCBZ62I-R7 Datasheet HTML 76Page - Analog Devices ADuC7023BCBZ62I-R7 Datasheet HTML 77Page - Analog Devices ADuC7023BCBZ62I-R7 Datasheet HTML 78Page - Analog Devices ADuC7023BCBZ62I-R7 Datasheet HTML 79Page - Analog Devices ADuC7023BCBZ62I-R7 Datasheet HTML 80Page - Analog Devices ADuC7023BCBZ62I-R7 Datasheet HTML 81Page - Analog Devices ADuC7023BCBZ62I-R7 Datasheet HTML 82Page - Analog Devices ADuC7023BCBZ62I-R7 Datasheet HTML 83Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 79 / 96 page
background image
Data Sheet
ADuC7023
| Page 79 of 96
IRQVEC Register
The IRQ interrupt vector register, IRQVEC, points to a memory
address containing a pointer to the interrupt service routine of
the currently active IRQ. This register should only be read when
an IRQ occurs and IRQ interrupt nesting has been enabled by
setting Bit 0 of the IRQCONN register.
IRQVEC Register
Name:
IRQVEC
Address:
0xFFFF001C
Default value: 0x00000000
Access:
Read only
Table 91. IRQVEC MMR Bit Designations
Bit
Type
Initial
Value
Description
31 to 23
Read only
0
Always read as 0.
22 to 7
R/W
0
IRQBASE register value.
6 to 2
Read only
0
Highest priority source. This is
a value between 0 and 21
representing the possible
interrupt sources. For example,
if the highest currently active
IRQ is Timer 2, then these bits
are [00100].
1 to 0
Reserved
0
Reserved bits.
Priority Registers
The IRQ interrupt vector register, IRQVEC, points to a memory
address containing a pointer to the interrupt service routine of
the currently active IRQ. This register should only be read when
an IRQ occurs and IRQ interrupt nesting has been enabled by
setting Bit 0 of the IRQCONN register.
Rev. E



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com