DSPIC33FJ06GS101TESLASHML datasheet(140/346 Pages) MICROCHIP

140 / 346 page

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

DS70318D-page 138

Preliminary

OSCCON: OSCILLATOR CONTROL REGISTER(1)

U-0

R-0

U-0

R/W-y

—COSC<2:0>

—NOSC<2:0>(2)

bit 15

bit 8

R/W-0

R-0

U-0

R/C-0

U-0

R/W-0

CLKLOCK

IOLOCK

LOCK

—CF

—

OSWEN

bit 7

bit 0

Legend:

y = Value set from Configuration bits on POR

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

Unimplemented:

Read as ‘0’

bit 14-12

COSC<2:0>:

Current Oscillator Selection bits (read-only)

000

= Fast RC oscillator (FRC)

001

= Fast RC oscillator (FRC) with PLL

010

= Primary oscillator (XT, HS, EC)

011

= Primary oscillator (XT, HS, EC) with PLL

100

= Reserved

101

= Low-Power RC oscillator (LPRC)

110

= Fast RC oscillator (FRC) with divide-by-16

111

= Fast RC oscillator (FRC) with divide-by-n

bit 11

Unimplemented:

Read as ‘0’

bit 10-8

NOSC<2:0>:

New Oscillator Selection bits(2)

000

= Fast RC oscillator (FRC)

001

= Fast RC oscillator (FRC) with PLL

010

= Primary oscillator (XT, HS, EC)

011

= Primary oscillator (XT, HS, EC) with PLL

100

= Reserved

101

= Low-Power RC oscillator (LPRC)

110

= Fast RC oscillator (FRC) with divide-by-16

111

= Fast RC oscillator (FRC) with divide-by-n

bit 7

CLKLOCK:

Clock Lock Enable bit

If clock switching is enabled and FSCM is disabled, (FOSC<FCKSM> = 0b01):

= Clock switching is disabled, system clock source is locked

= Clock switching is enabled, system clock source can be modified by clock switching

bit 6

IOLOCK:

Peripheral Pin Select Lock bit

= Peripherial pin select is locked, write to Peripheral Pin Select registers not allowed

= Peripherial pin select is not locked, write to Peripheral Pin Select registers allowed

bit 5

LOCK:

PLL Lock Status bit (read-only)

= Indicates that PLL is in lock, or PLL start-up timer is satisfied

= Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled

bit 4

Unimplemented:

Read as ‘0’

Note 1:

Writes to this register require an unlock sequence. Refer to Section 42. “Oscillator (Part IV)” (DS70307)

in the “dsPIC33F Family Reference Manual” (available from the Microchip website) for details.

Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.

This applies to clock switches in either direction. In these instances, the application must switch to FRC mode

as a transition clock source between the two PLL modes.

DSPIC33FJ06GS101TE/ML 데이터시트(PDF) 140 Page - Microchip Technology

DSPIC33FJ06GS101TE/ML 데이터시트(HTML) 140 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL