AD9963BCPZ datasheet(19/61 Pages) AD

19 / 61 page

Data Sheet

AD9961/AD9963

Rev. A | Page 19 of 60

THEORY OF OPERATION

The AD9961/AD9963 are targeted to cover the mixed-signal

front-end needs of multiple wireless communications systems.

They feature a receive path that consists of dual 10-/12-bit

receive ADCs and a transmit path that consists of dual

10-/12-bit transmit DACs (TxDAC). The AD9961/AD9963

integrate additional functionality typically required in most

systems, such as power scalability, Tx gain control, and clock

multiplication circuitry.

The AD9961/AD9963 minimize both size and power

consumption to address the needs of a range of applications

from the low power portable market to the high performance

femto base station market. The part is provided in a 72-lead

lead frame chip scale package (LFCSP) that has a footprint of

only 10 mm × 10 mm. Power consumption can be optimized to

suit the particular application by incorporating power-down

controls, low power ADC modes, and TxDAC power scaling.

In full duplex mode, the AD9961/AD9963 use two 12-bit buses,

along with qualifying clock signals, to transfer Rx path data and

Tx path data. These two buses support either single data rate or

double data rate data transfers. The data bus, along with many

other device options, is configurable through the serial port by

writing internal registers. The device can also be used in a

single-port, half-duplex configuration.

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