4116R-R2R-503 datasheet(56/62 Pages) BOURNS

56 / 62 page

Specifications are subject to change without notice.

332

Application Guidelines

Termination of address and control lines is typically accom-

plished with low-valued resistors placed in series at the driver

output. Selection of the proper resistance value is performed in

two steps: approximation of the proper resistance using trans-

mission line equations, and secondly, through trial and error,

changing the resistance value to account for real world devia-

tions such as PCB vias and bends.

The appropriate transmission line equations are as

follows:

Zo = characteristic line impedance

(microstrip)

5.98h

ohms

√ er + 1.41

(

0.8w + t

)

Td = propagation delay of the line

= 1.017

√0.475e

r + 0.67 ns/in.

Co = trace capacitance = 1000 (Td/Zo) pF/in.

Cd = equivalent trace capacitance associated with

each DRAM. It takes 0.5 inch to interconnect

one DRAM.

= 3.5pF/0.5 in. = 7 pF/in.

Zo’ = effective characteristic impedance, accounting

for capacitive loading of the DRAMs.

√1 + C

d/Co

Td’ = effective propagation delay, accounting for the

capacitive loading of the DRAMs

Td = Td √1 + Cd/Co

where er = relative dielectric constant of the PCB’s glass

epoxy layer

= distance from the trace to the ground plane

= width of trace

= thickness of trace

(Ref. MMI Systems Design Handbook, pp. 10-5 and 10-6.)

For example, for a trace with the following characteristics:

= 5 (for G10 glass epoxy)

= 30 mils

= 15 mils

= 3 mils

then, Zo = 85 ohms

Td = 0.15 ns/in.

Co = 1.76 pF/in.

Zo’ = 38 ohms

Td’ = 0.35 ns/in.

Thus on a theoretical basis, the design will require the resis-

tance of 38 ohms to match the trace impedance of the PCB.

However, the actual impedance will differ from this theoretical

value due to the non-ideal characteristics of the PCB trace

geometry (i.e., bends, curves and vias in the trace), as well as

the manufacturing variations inherent in the components and

materials. Therefore, a trial-and-error process must be employed

in order to optimize the value of the damping resistor.

The procedure involves selecting various values around the

calculated value and observing the resulting waveforms on an

oscilloscope. Choose the value that best balances the reduction

in ringing/reflection and the reduction in speed: a large resis-

tance value provides better damping, but will also add delay by

slowing the edge rate. Typically, resistance values for memory

damping will be in the range of 10 ohms to 50 ohms, with the

most common values in the 20 ohm to 30 ohm range.

Since memory damping is a type of series termination, distrib-

uted loading along the line will not be possible. That is, the

entire lumped load must be located at the end of the line, with

no other loads along the signal path. This will guarantee that the

waveform will remain undisturbed as it travels along the line. For

related reasons, the placement of the series damping resistor

should be as close to the driving device as possible.

DRAM Applications

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