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Chapter 1: Cyclone IV FPGA Device Family Overview

Cyclone IV Device Family Features

Cyclone IV Device Handbook,

November 2011

Altera Corporation

Volume 1

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Cyclone IV GX devices offer up to eight high-speed transceivers that provide:

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Data rates up to 3.125 Gbps

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8B/10B encoder/decoder

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8-bit or 10-bit physical media attachment (PMA) to physical coding sublayer

(PCS) interface

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Byte serializer/deserializer (SERDES)

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Word aligner

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Rate matching FIFO

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TX bit slipper for Common Public Radio Interface (CPRI)

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Electrical idle

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Dynamic channel reconfiguration allowing you to change data rates and

protocols on-the-fly

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Static equalization and pre-emphasis for superior signal integrity

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150 mW per channel power consumption

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Flexible clocking structure to support multiple protocols in a single transceiver

block

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Cyclone IV GX devices offer dedicated hard IP for PCI Express (PIPE) (PCIe)

Gen 1:

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×1, ×2, and ×4 lane configurations

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End-point and root-port configurations

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Up to 256-byte payload

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One virtual channel

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2 KB retry buffer

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4 KB receiver (Rx) buffer

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Cyclone IV GX devices offer a wide range of protocol support:

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PCIe (PIPE) Gen 1 ×1, ×2, and ×4 (2.5 Gbps)

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Gigabit Ethernet (1.25 Gbps)

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CPRI (up to 3.072 Gbps)

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XAUI (3.125 Gbps)

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Triple rate serial digital interface (SDI) (up to 2.97 Gbps)

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Serial RapidIO (3.125 Gbps)

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Basic mode (up to 3.125 Gbps)

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V-by-One (up to 3.0 Gbps)

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DisplayPort (2.7 Gbps)

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Serial Advanced Technology Attachment (SATA) (up to 3.0 Gbps)

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OBSAI (up to 3.072 Gbps)