ThunderLAN

™ TNETE100A

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN

SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996

9

POST OFFICE BOX 1443

Pin Functions (Continued)

PIN

TYPE†

DESCRIPTION

NAME

NO.

TYPE†

DESCRIPTION

POWER

VDDI

6, 14,

34, 48,

122, 136,

142

PWR

PCI VDD pins. VDDI pins provide power for the PCI I/O pin drivers. Connect VDDI pins to a 5-V power

supply when using 5-V signals on the PCI bus. Connect VDDI pins to a 3-V power supply when using

3-V signals on the PCI bus

VDDL

22, 37,

58, 70,

79, 84,

94, 130

PWR

Logic VDD pins (5 V). VDDL pins provide power for internal TNETE100A logic, and they should always

be connected to a 5-V power supply.

VDDOSC

115

PWR

Analog power pin. VDDOSC is the 5-V power for the crystal oscillator circuit.

VDDR

104

107

PWR

Analog power pin. VDDR is the 5-V power for the receiver circuitry.

VDDT

96

PWR

Analog power pin. VDDT is the 5-V power for the transmitter circuitry.

VDDVCO

117

PWR

Analog power pin. VDDVCO is the 5-V power for the voltage controller oscillator (VCO) and filter input.

VSSI

3, 10, 26,

31, 40,

52, 67,

88, 127,

139

PWR

PCI I / O ground pins

VSSL

18, 44,

63, 75,

92, 133

PWR

Logic ground pins

VSSOSC

112

PWR

Analog power pin. Ground for crystal oscillator circuit

VSSR

102

110

PWR

Analog power pin. Ground for receiver circuitry

VSST

101

PWR

Analog power pin. Ground for transmitter circuitry

VSSVCO

119

PWR

Analog power pin. Ground for VCO and filter input

† PWR = power

architecture

The major blocks of the TNETE100A include the PCI interface (PCIIF), protocol handler (PH), media

independent interface (MII), physical layer (PHY), FIFO pointer registers (FPREGS), FIFO SRAM (FSRAM),

and a test-access port (TAP). The functionality of these blocks is described in the following sections.

PCI interface (PCIIF)

The TNETE100A PCIIF contains a byte-aligning DMA controller that allows frames to be fragmented into any

byte length and transferred to any byte address while supporting 32-bit data streaming. For multipriority

networks, it can provide multiple data channels, each with separate lists, commands, and status. Data for the

channels is passed to and from the PH by way of circular buffer FIFOs in the SRAM, controlled through FIFO

registers. The configuration EEPROM interface (CEI), BIOS ROM /LED driver interface (BRI), configuration and

I / O memory registers (CIOREGS), and DMA controller are subblocks of the PCIIF. The features of these

subblocks are described in the following subsections.

configuration EEPROM interface (CEI)

The CEI provides a means for autoconfiguration of the PCI configuration registers. Certain registers in the PCI

configuration space can be loaded using the CEI. Autoconfiguration allows builders of TNETE100A-based

systems to customize the contents of these registers to identify their own system, rather than to use the TI

defaults. The EEPROM is read at power up and can then be read from, and written to, under program control.