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TMS320DM641GDK600 데이터시트(PDF) 39 Page - Texas Instruments |
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TMS320DM641GDK600 데이터시트(HTML) 39 Page - Texas Instruments |
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39 / 179 page ![]() Pin Assignments 39 June 2003 − Revised October 2010 SPRS222F VP0D[0]/CLKX0 VP0D[1]/FSX0 VP0D[2]/DX0 VP0D[3]/CLKS0 VP0D[4]/DR0 VP0D[5]/FSR0 VP0D[6]/CLKR0 VP0D[7] Capture/Display Buffer (2560 Bytes) VP0CLK0 VP0CLK1 VP0CTL0 VP0CTL1 VP0CTL2 Timing and Control Logic Video Port 0 (VP0) Channel A† † Channel A supports: BT.656 (8-bit) display pipeline mode and BT.656 (8-bit) capture pipeline mode [TSI (8-bit) capture pipeline mode]. STCLK Figure 1−6. Peripheral Signals (Continued) |
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