LTM4607 datasheet(24/30 Pages) LINER

24 / 30 page

LTC3780

3780ff

For more information www.linear.com/LTC3780

applicaTions inForMaTion

Double-check the TJ in the MOSFET with 70°C ambient

temperature:

TJ = 70°C + 1.94W • 40°C/W = 147.6°C

The maximum power dissipation of switch B occurs in

buck mode. Assuming a junction temperature of TJ = 80°C

with

ρ80°C = 1.2, the power dissipation at VIN = 18V is:

PB,BUCK =

18 –12

•52 •1.2•0.009 = 90mW

Double-check the TJ in the MOSFET at 70°C ambient

temperature:

TJ = 70°C + 0.09W • 40°C/W = 73.6°C

ThemaximumpowerdissipationofswitchCoccursinboost

mode.AssumingajunctiontemperatureofTJ=110°Cwith

ρ110°C = 1.4, the power dissipation at VIN = 5V is:

PC,BOOST =

12– 5

(

)•12

•52 •1.4•0.009

+ 2•123 •

•150p• 400k

= 1.27W

Double-check the TJ in the MOSFET at 70°C ambient

temperature:

TJ = 70°C + 1.08W • 40°C/W = 113°C

The maximum power dissipation of switch D occurs

in boost mode when its duty cycle is higher than 50%.

Assuming a junction temperature of TJ = 100°C with

ρ100°C = 1.35, the power dissipation at VIN = 5V is:

DBOOST

••

•. •.









51 35 0 009 073

Double-check the TJ in the MOSFET at 70°C ambient

temperature:

TJ = 70°C + 0.73W • 40°C/W = 99°C

CIN is chosen to filter the square current in buck mode. In

this mode, the maximum input current peak is:

IN PEAK MAXBUCK

•









A low ESR (10mΩ) capacitor is selected. Input voltage

ripple is 57mV (assuming ESR dominate ripple).

COUT is chosen to filter the square current in boost mode.

In this mode, the maximum output current peak is:

IOUT PEAK MAXBOOST

••









10 66A

A low ESR (5mΩ) capacitor is suggested. This capacitor

will limit output voltage ripple to 53mV (assuming ESR

dominate ripple).

PC Board Layout Checklist

The basic PC board layout requires a dedicated ground

plane layer. Also, for high current, a multilayer board

provides heat sinking for power components.

• The ground plane layer should not have any traces and

it should be as close as possible to the layer with power

MOSFETs.

• Place CIN, switch A, switch B and D1 in one com-

pact area. Place COUT, switch C, switch D and D2 in

one compact area. One layout example is shown in

Figure 10.

GND

VOUT

COUT

RSENSE

3780 F10

SW2

SW1

VIN

CIN

LTC3780

CKT

Figure 10. Switches Layout

LTM4607 데이터시트(PDF) 24 Page - Linear Technology

LTM4607 데이터시트(HTML) 24 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

데이터시트 다운로드

링크 URL