QUICC

TIME

SLOT

ASSIGNER

SCC

SCC

SCC

SCC

SMC

SMC

ANY COMBINATION OF SCCs

AND SMCs MAY BE

CONNECTED TO ANY TDM.

TDM BUS 1

TDM BUS 2

NOTE: Two TDM buses may be simultaneously supported

with the time slot assigner.

Figure 6. Dual TDM Bus Implementation

QUICC Serial Configuration Examples

Figure 7 shows a general-purpose application that includes Ethernet, AppleTalk, an HDLC connection to a

T1 line, an HDLC connection to frame relay, a UART debug monitor port, a totally transparent data stream

port, and an SPI connection to a serial EEPROM.

QUICC

SCC1

SCC2

SCC3

SCC4

SMC2

SPI

ETHERNET

RS-422

APPLE TALK

T1 LINE

TRANSCEIVER

X.25 (HDLC)

RS-232

FRAME RELAY (HDLC)

RS-232

UART

SERIAL

EEPROM

SYSTEM

BUS

TIME

SLOT

ASSIGNER

FREESCALE

SIA

TRANSCEIVER

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com