MCZ33903CD3EKSLASHR2 datasheet(69/106 Pages) FREESCALE

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Analog Integrated Circuit Device Data



Freescale Semiconductor

33903/4/5

SERIAL PERIPHERAL INTERFACE

DETAIL OF CONTROL BITS AND REGISTER MAPPING

INIT REGISTERS

Note: these registers can be written only in INIT mode

Table 17. Initialization Regulator Registers, INIT REG (note: register can be written only in INIT mode)

MOSI First Byte [15-8]

[b_15 b_14] 0_0101 [P/N]

MOSI Second Byte, bits 7-0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

01 00 _ 101 P

I/O-x sync

VDDL rst[1]

VDDL rst[0]

VDD rstD[1]

VDD rstD[0]

VAUX5/3

Cyclic on[1]

Cyclic on[0]

Default state

Condition for default

POR

Bit

Description

I/O-x sync - Determine if I/O-1 is sensed during I/O-0 activation, when cyclic sense function is selected

I/O-1 sense anytime

I/O-1 sense during I/O-0 activation

b6, b5

VDDL RST[1] VDDL RST[0] - Select the VDD under-voltage threshold, to activate RST pin and/or INT

Reset at approx 0.9 VDD.

INT at approx 0.9 VDD, Reset at approx 0.7 VDD

Reset at approx 0.7 VDD

Reset at approx 0.9 VDD.

b4, b3

VDD RSTD[1] VDD RSTD[0] - Select the RST pin low lev duration, after VDD rises above the VDD under-voltage threshold

1.0 ms

5.0 ms

10 ms

20 ms

[VAUX 5/3] - Select Vauxilary output voltage

VAUX = 3.3 V

VAUX = 5.0 V

b1, b0

Cyclic on[1] Cyclic on[0] - Determine I/O-0 activation time, when cyclic sense function is selected

200

s (typical value. Ref. to dynamic parameters for exact value)

400

s (typical value. Ref. to dynamic parameters for exact value)

800

s (typical value. Ref. to dynamic parameters for exact value)

1600

s (typical value. Ref. to dynamic parameters for exact value)

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