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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AD8381 데이터시트(PDF) 3 Page - Analog Devices |
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AD8381 데이터시트(HTML) 3 Page - Analog Devices |
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3 / 16 page  REV. B –3– AD8381 TIMING CHARACTERISTICS Parameter Conditions Min Typ Max Unit t1 CLK to Data Setup Time CLK Rise and Fall Time = 5 ns 0 ns t2 CLK to Data Hold Time CLK Rise and Fall Time = 5 ns 5 ns t3 CLK to STSQ Setup Time CLK Rise and Fall Time = 5 ns 0 ns t4 CLK to STSQ Hold Time CLK Rise and Fall Time = 5 ns 5 ns t5 CLK to XFR Setup Time CLK Rise and Fall Time = 5 ns 0 ns t6 CLK to XFR Hold Time CLK Rise and Fall Time = 5 ns 5 ns t7 CLK to VID Delay 13.5 15.5 17.5 ns DB (0:9) CLK STSQ, XFR –1 0 t 3,t5 t 4,t6 t 1 t 2 Figure 1. Timing Requirement E/O = High DB (0:9) CLK STSQ –1 0 XFR t 1 t 2 t 3 t 4 t 5 t 6 Figure 2. Timing Requirements E/O = Low CLK XFR VIDx t 7 Figure 3. Output Timing |
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