전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

SMP18FPZ 데이터시트(PDF) 7 Page - Analog Devices

부품명 SMP18FPZ
상세설명  Octal Sample-and-Hold with Multiplexed Input
PDF  8 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

SMP18FPZ 데이터시트(HTML) 7 Page - Analog Devices

  SMP18FPZ Datasheet HTML 1Page - Analog Devices SMP18FPZ Datasheet HTML 2Page - Analog Devices SMP18FPZ Datasheet HTML 3Page - Analog Devices SMP18FPZ Datasheet HTML 4Page - Analog Devices SMP18FPZ Datasheet HTML 5Page - Analog Devices SMP18FPZ Datasheet HTML 6Page - Analog Devices SMP18FPZ Datasheet HTML 7Page - Analog Devices SMP18FPZ Datasheet HTML 8Page - Analog Devices  
Zoom Inzoom in Zoom Outzoom out
 7 / 8 page
background image
SMP18
REV. C
–7–
APPLICATION TIPS
All unused digital inputs should be connected to logic LOW.
For analog inputs that may become temporarily disconnected, a
resistor to VDD, VSS or analog ground should be used with a
value ranging from 200 k
Ω to 1 MΩ.
Do not apply signals to the SMP18 with power off unless the in-
put current is limited to less than 10 mA.
TYPICAL APPLICATIONS
An 8-Channel Multiplexed D/A Converter
Figure 1 illustrates a typical demultiplexing function of the
SMP18. It is used to sample-and-hold eight different output
voltages corresponding to eight different digital codes from a
D/A converter. The SMP18’s droop rate of 40 mV/s requires a
refresh once every 250 ms before the voltage drifts beyond
1/2 LSB accuracy (1 LSB of an 8-bit DAC is equivalent to
19.5 mV out of a full-scale voltage of 5 V). For a 10-bit DAC
the refresh rate must be less than 60 ms, and for a 12-bit
system, 15 ms. This implementation is very cost effective com-
pared to using multiple DACs as the number of output channels
increases.
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SMP18
13
14
15
12
1
2
4
5
3
16
6
7
8
9
10
11
+12V
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
3
15
1
5
16
17
4
+12V
+5V
REF02
+12V
VREFAVDD
VOA
VZ
GND
WR
CS
DAC8228
A
B
C
ADDRESS
DECODE
ADDRESS
BUS
DIGITAL
INPUTS
WR
DGND
INH
0.1µF
PIN 9
C
PIN 10
B
PIN 11
A
PIN 6
INH
CH
PIN
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
X
0
0
0
0
0
0
0
0
1
0
1
2
3
4
5
6
7
NONE
13
14
15
12
1
5
2
4
–
CHANNEL DECODING
Figure 1. 8-Channel Multiplexed D/A Converter



Html Pages

1 2 3 4 5 6 7 8


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com