WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)

Dout

Din

Data Valid

(4)

High-Z

WE#

CE#

Address

(4)

WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)

Dout

Din

Data Valid

(4)

High-Z

WE#

CE#

Address

Notes :

1.WE#, CE# must be high during all address transitions.

2.A write occurs during the overlap of a low CE#, low WE#.

placed on the bus.

4.During this period, I/O pins are in the output state, and input signals must not be applied.

5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.

®

512K X 8 BIT LOW POWER CMOS SRAM

OCTOBER 2007

AS6C4008

10/OCTOBER/07, V.1.1

Alliance Memory Inc.

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