TMP86FH47BUG datasheet(13/218 Pages) TOSHIBA

13 / 218 page

Table of Contents

Difference among product (TMP86xx46 Series)

TMP86FH47BUG

1.1 Features......................................................................................................................................1

1.2 Pin Assignment..........................................................................................................................3

1.3 Block Diagram...........................................................................................................................4

1.4 Pin Names and Functions..........................................................................................................5

2. Operational Description

2.1 CPU Core Functions ................................................................................................................7

2.1.1

Memory Address Map .......................................................................................................................................................7

2.1.2

Program Memory (Flash) ...................................................................................................................................................7

2.1.3

Data Memory (RAM) .........................................................................................................................................................7

2.2 System Clock Controller ..........................................................................................................8

2.2.1

Clock Generator .................................................................................................................................................................8

2.2.2

Timing Generator .............................................................................................................................................................10

2.2.2.1

Configuration of timing generator

2.2.2.2

Machine cycle

2.2.3

Operation Mode Control Circuit ......................................................................................................................................11

2.2.3.1

Single-clock mode

2.2.3.2

Dual-clock mode

2.2.3.3

STOP mode

2.2.4

Operating Mode Control ..................................................................................................................................................16

2.2.4.1

STOP mode

2.2.4.2

IDLE1/2 mode and SLEEP1/2 mode

2.2.4.3

IDLE0 and SLEEP0 modes (IDLE0, SLEEP0)

2.2.4.4

SLOW mode

2.3 Reset Circuit ...........................................................................................................................29

2.3.1

External Reset Input .........................................................................................................................................................29

2.3.2

Address trap reset .............................................................................................................................................................30

2.3.3

Watchdog timer reset .......................................................................................................................................................30

2.3.4

System clock reset ............................................................................................................................................................30

3. Interrupt Control Circuit

3.1 Interrupt latches (IL15 to IL2) ...............................................................................................31

3.2 Interrupt enable register (EIR) ...............................................................................................32

3.2.1

Interrupt master enable flag (IMF) ..................................................................................................................................32

3.2.2

Individual interrupt enable flags (EF15 to EF4) .............................................................................................................32

3.3 Interrupt Source Selector (INTSEL).......................................................................................35

3.4

Interrupt Sequence ................................................................................................................35

3.4.1

Interrupt acceptance processing is packaged as follows. ................................................................................................35

3.4.2

Saving/restoring general-purpose registers ......................................................................................................................36

3.4.2.1

Using PUSH and POP instructions

3.4.2.2

Using data transfer instructions

3.4.3

Interrupt return .................................................................................................................................................................38

TMP86FH47BUG 데이터시트(PDF) 13 Page - Toshiba Semiconductor

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