AD5381BSTZ-5 datasheet(32/40 Pages) AD

32 / 40 page

AD5381

Data Sheet

Rev. D | Page 32 of 40

AD5381 to PIC16C6x/7x

The PIC16C6x/7x synchronous serial port (SSP)is configured

as an SPI master with the ClockPolarity Bit = 0. This is done

by writing to the synchronousserial port control register

(SSPCON). See the PIC16/17 microcontroller user manual.

In this example I/O, Port RA1 is being used to pulse SYNC

and enable the serial port of the AD5381. This microcontroller

transfers only eight bits of dataduring each serial transfer

operation; therefore,threeconsecutiveread/write operations

may be needed depending on the mode. Figure 36 showsthe

connection diagram.

PIC16C6X/7X

AD5381

SDI/RC4

SDO/RC5

SCK/RC3

RA1

SDO

RESET

SER/PAR

DIN

SCLK

SYNC

SPI/I2C

DVDD

Figure 36. AD5381-to-PIC16C6x/7x Interface

AD5381 to 8051

The AD5381 requires a clocksynchronized to the serial data.

The 8051 serial interface must thereforebe operated in Mode 0.

In this mode, serial data enters and exits through RxD, and a

shift clock is output on TxD. Figure 37 shows howthe 8051 is

connected to the AD5381. Because the AD5381 shifts data out

on the rising edge of the shift clock and latches data in on the

falling edge, the shift clock must be inverted.The AD5381

requires its data to be MSBfirst. Since the 8051 outputs the

LSB first, the transmit routine must take this into account.

8XC51

AD5381

RxD

TxD

P1.1

SDO

RESET

SER/PAR

DIN

SCLK

SYNC

SPI/I2C

DVDD

Figure 37. AD5381-to-8051 Interface

AD5381 to ADSP-2101/ADSP-2103

Figure 38 shows a serial interface between the AD5381 and the

ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should

be set up to operate in SPORT transmit alternateframing mode.

The ADSP-2101/ADSP-2103 SPORT is programmedthrough

the SPORT control registerand configuredas follows: internal

clock operation,active low framing, and 16-bit word length.

Transmission is initiated by writing a word to the Tx register

after the SPORT has been enabled.

ADSP-2101/

ADSP-2103

AD5381

SCK

TFS

RFS

SDO

RESET

SER/PAR

DIN

SCLK

DVDD

SPI/I2C

SYNC

Figure 38. AD5381-to-ADSP-2101/ADSP-2103 Interface

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