AD7738 datasheet(4/28 Pages) AD

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REV. 0

–4–

AD7738

TIMING SPECIFICATIONS1, 2, 3

(AVDD = 5 V

5%; DVDD = 2.7 V to 3.6 V or 5 V

5%; Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted.)

Parameter

Min

Typ

Max

Unit

Test Conditions/Comment

MASTER CLOCK RANGE

6.144

MHz

SYNC Pulsewidth

500

RESET Pulsewidth

READ OPERATION

0ns

CS Falling Edge to SCLK Falling Edge Setup Time

SCLK Falling Edge to Data Valid Delay

060

DVDD of 4.75 V to 5.25 V

080

DVDD of 2.7 V to 3.3 V

t5A

4, 5

CS Falling Edge to Data Valid Delay

060

DVDD of 4.75 V to 5.25 V

080

DVDD of 2.7 V to 3.3 V

SCLK High Pulsewidth

SCLK Low Pulsewidth

0ns

CS Rising Edge after SCLK Rising Edge Hold Time

Bus Relinquish Time after SCLK Rising Edge

WRITE OPERATION

t11

0ns

CS Falling Edge to SCLK Falling Edge Setup

t12

Data Valid to SCLK Rising Edge Setup Time

t13

Data Valid after SCLK Rising Edge Hold Time

t14

SCLK High Pulsewidth

t15

SCLK Low Pulsewidth

t16

0ns

CS Rising Edge after SCLK Rising Edge Hold Time

NOTES

1Sample tested during initial release to ensure compliance.

2All input signals are specified with tr = tf = 5 ns (10% to 90% of DV

DD) and timed from a voltage level of 1.6 V.

3See Figures 1 and 2.

4These numbers are measured with the load circuit of Figure 3 and defined as the time required for the output to cross the V

OL or VOH limits.

5This specification is relevant only if CS goes low while SCLK is low.

6These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 3.

The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing

characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances.

Specifications are subject to change without notice.

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