AD9517-0ASLASHPCBZ datasheet(78/80 Pages) AD

78 / 80 page

AD9517-0

Data Sheet

Rev. E | Page 78 of 80

CMOS CLOCK DISTRIBUTION

The AD9517 provides four clock outputs (OUT4 to OUT7)

that are selectable as either CMOS or LVDS level outputs.

When selected as CMOS, each output becomes a pair of CMOS

outputs, each of which can be individually turned on or off and

set as noninverting or inverting. These outputs are 3.3 V CMOS

compatible.

Whenever single-ended CMOS clocking is used, some of the

following general guidelines should be used.

Point-to-point nets should be designed such that a driver has

only one receiver on the net, if possible. This allows for simple

termination schemes and minimizes ringing due to possible

mismatched impedances on the net.

Series termination at the source is generally required to provide

transmission line matching and/or to reduce current transients

at the driver. The value of the resistor is dependent on the board

design and timing requirements (typically 10 Ω to 100 Ω is used).

CMOS outputs are also limited in terms of the capacitive load

or trace length that they can drive. Typically, trace lengths of less

than 3 inches are recommended to preserve signal rise/fall times

and preserve signal integrity.

CMOS

10Ω

60.4Ω

(1.0 INCH)

MICROSTRIP

Figure 75. Series Termination of CMOS Output

Termination at the far end of the PCB trace is a second option.

The CMOS outputs of the AD9517 do not supply enough current

to provide a full voltage swing with a low impedance resistive,

far-end termination, as shown in Figure 76. The far-end

termination network should match the PCB trace impedance and

provide the desired switching point. The reduced signal swing

may still meet receiver input requirements in some applications.

This can be useful when driving long trace lengths on less

critical nets.

CMOS

10Ω

50Ω

100Ω

Figure 76. CMOS Output with Far-End Termination

Because of the limitations of single-ended CMOS clocking,

consider using differential outputs when driving high speed

signals over long traces. The AD9517 offers both LVPECL and

LVDS outputs that are better suited for driving long traces

where the inherent noise immunity of differential signaling

provides superior performance for clocking converters.

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