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PIC12F635ESL 데이터시트(PDF) 85 Page - Microchip Technology

부품명 PIC12F635ESL
상세설명  PIC12F635/PIC16F636/639 Data Sheet
PDF  234 Pages
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제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

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© 2007 Microchip Technology Inc.
DS41232D-page 83
PIC12F635/PIC16F636/639
7.11
Comparator Voltage Reference
The Comparator Voltage Reference module provides
an internally generated voltage reference for the
comparators. The following features are available:
• Independent from Comparator operation
• Two 16-level voltage ranges
• Output clamped to VSS
• Ratiometric with VDD
• Fixed Voltage Reference
The VRCON register (Register 7-5) controls the
Voltage Reference module shown in Figure 7-10.
7.11.1
INDEPENDENT OPERATION
The comparator voltage reference is independent of
the comparator configuration. Setting the VREN bit of
the VRCON register will enable the voltage reference.
7.11.2
OUTPUT VOLTAGE SELECTION
The
CVREF voltage reference has 2 ranges with 16
voltage levels in each range. Range selection is
controlled by the VRR bit of the VRCON register. The
16 levels are set with the VR<3:0> bits of the VRCON
register.
The CVREF output voltage is determined by the following
equations:
EQUATION 7-1:
CVREF OUTPUT VOLTAGE
(INTERNAL CVREF)
EQUATION 7-2:
CVREF OUTPUT VOLTAGE
(EXTERNAL CVREF)
The full range of VSS to VDD cannot be realized due to
the construction of the module. See Figure 7-10.
7.11.3
OUTPUT CLAMPED TO VSS
The CVREF output voltage can be set to Vss with no
power consumption by configuring VRCON as follows:
•VREN = 0
•VRR = 1
•VR<3:0> = 0000
This allows the comparator to detect a zero-crossing
while not consuming additional CVREF module current.
7.11.4
OUTPUT RATIOMETRIC TO VDD
The comparator voltage reference is VDD derived and
therefore, the CVREF output changes with fluctuations in
VDD. The tested absolute accuracy of the Comparator
Voltage Reference can be found in Section 15.0 “Elec-
trical Specifications”.
VRR
1 (low range):
=
VRR
0 (high range):
=
CVREF
(VDD/4) +
=
CVREF
(VR<3:0>/24)
VDD
×
=
(VR<3:0>
VDD/32)
×
VRR
1 (low range):
=
VRR
0 (high range):
=
CVREF
(VLADDER/4) +
=
CVREF
(VR<3:0>/24)
VLADDER
×
=
(VR<3:0>
VLADDER/32)
×
VLADDER
VDD
=
or ([VREF+] - [VREF-]) or VREF+



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