3972

DUAL DMOS FULL-BRIDGE

MICROSTEPPING PWM MOTOR DRIVER

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

2

FUNCTIONAL BLOCK DIAGRAM

Copyright © 2000, Allegro MicroSystems, Inc.

CONTROL

LOGIC

REGULATOR

UVLO AND

FAULT

DETECT

OUT

1A

SENSE

1

GATE

DRIVE

CHARGE PUMP

V

REG

CP1

CP2

V

CP

V

BB1

BANDGAP

OSC

SERIAL

PORT

CLOCK

DATA

STROBE

OUT

1B

0.22

µF

+-

V

DD

PHASE 1/2

SYNC. RECT. MODE

SYNC. RECT. DISABLE

MODE 1/2

0.22

µF

0.22

µF

REF

OUT

2A

V

BB2

OUT

2B

SENSE

2

PROGRAMMABLE

PWM TIMER

FIXED-OFF

BLANK

MIXED DECAY

PROGRAMMABLE

PWM TIMER

FIXED-OFF

BLANK

MIXED DECAY

6-BIT

LINEAR

DAC

+-

SENSE

1

V

CP

2 V

2 V

GROUND

MUX

OSCILATOR

OSC SELECT/

DIVIDER

BUFFER

0.1

µF

SLEEP

DMOS H-BRIDGE

DMOS H-BRIDGE

15

14

24

11

12

10

23

13

17

21

16

20

8

4

9

5

1

3

2

22

6

7

18 19

LOAD

SUPPLY

LOGIC

SUPPLY

0.1

µF

Dwg. FP-050-1

6

6

6-BIT

LINEAR

DAC