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GAL22V10D-25LS 데이터시트(PDF) 11 Page - Lattice Semiconductor

부품명 GAL22V10D-25LS
상세설명  Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet.
PDF  23 Pages
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제조업체  LATTICE [Lattice Semiconductor]
홈페이지  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

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Specifications GAL22V10
9
tpd
A
Input or I/O to Comb. Output
1
10
3
15
3
20
3
25
ns
tco
A
Clock to Output Delay
1
7
2
8
2
10
2
15
ns
tcf2
—
Clock to Feedback Delay
—
2.5
—
2.5
—
8
—
13
ns
tsu
—
Setup Time, Input or Fdbk before Clk↑
6
—
10
—
12
—
15
—
ns
th
—
Hold Time, Input or Fdbk after Clk↑
0—
0—
0
—
0
—
ns
A
Maximum Clock Frequency with
83.3
—
55.5
—
41.6
—
33.3
—
MHz
External Feedback, 1/(tsu + tco)
fmax3
A
Maximum Clock Frequency with
110
—
80
—
45.4
—
35.7
—
MHz
Internal Feedback, 1/(tsu + tcf)
A
Maximum Clock Frequency with
125
—
83.3
—
50
—
38.5
—
MHz
No Feedback
twh
—
Clock Pulse Duration, High
4
—
6
—
10
—
13
—
ns
twl
—
Clock Pulse Duration, Low
4
—
6
—
10
—
13
—
ns
ten
B
Input or I/O to Output Enabled
1
10
3
15
3
20
3
25
ns
tdis
C
Input or I/O to Output Disabled
1
9
3
15
3
20
3
25
ns
tar
A
Input or I/O to Asynch. Reset of Reg.
1
13
3
20
3
25
3
25
ns
tarw
—
Asynch. Reset Pulse Duration
8
—
15
—
20
—
25
—
ns
tarr
—
Asynch. Reset to Clk↑ Recovery Time
8
—
10
—
20
—
25
—
ns
tspr
—
Synch. Preset to Clk↑ Recovery Time
8
—
10
—
14
—
15
—
ns
Specifications GAL22V10D
-10
MIN. MAX.
-25
MIN. MAX.
-20
MIN. MAX.
-15
MIN. MAX.
Over Recommended Operating Conditions
UNITS
1) Refer to Switching Test Conditions section.
2) Calculated from fmax with internal feedback. Refer to fmax Description section.
3) Refer to fmax Description section.
SYMBOL
PARAMETER
MAXIMUM*
UNITS
TEST CONDITIONS
C
I
Input Capacitance
8
pF
V
CC = 5.0V, VI = 2.0V
C
I/O
I/O Capacitance
8
pF
V
CC = 5.0V, VI/O = 2.0V
*Characterized but not 100% tested.
PARAM.
TEST
COND.1
DESCRIPTION
COM / IND
IND
COM / IND
COM / IND
Capacitance (T
A = 25
°C, f = 1.0 MHz)
AC Switching Characteristics



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