AD7809BST datasheet(5/28 Pages) AD

5 / 28 page

AD7804/AD7805/AD7808/AD7809

–5–

REV. A

AD7805/AD7809 TIMING CHARACTERISTICS1 (V

DD = 3.3 V

10% to 5 V

10%; AGND = DGND = 0 V; Reference

= Internal Reference. All specifications TMIN to TMAX unless otherwise noted.)

Limit at TMIN, TMAX

Parameter

All Versions

Unit

Description

ns min

Mode Valid to Write Setup Time

4.5

ns min

Mode Valid to Write Hold Time

ns min

Address Valid to Write Setup Time

4.5

ns min

Address Valid to Write Hold Time

ns min

Data Setup Time

4.5

ns min

Data Hold Time

t6A

ns min

LDAC Valid to Write Hold Time

ns min

Chip Select to Write Setup Time

ns min

Chip Select to Write Hold Time

ns min

Write Pulsewidth

t10

100

ns min

Time Between Successive Writes

t11

ns min

LDAC, CLR Pulsewidth

t12

100

ns min

Write to

LDAC Setup Time

NOTE

1Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns and

timed from a voltage of (VIL + VIH)/2.

Specifications subject to change without notice.

MODE

DATA

LDAC 2

CLR

LDAC 1

1TIMING REQUIREMENTS FOR SYNCHRONOUS LDAC UPDATE OR LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED.

2TIMING REQUIREMENTS FOR ASYNCHRONOUS LDAC UPDATE.

A0, A1, A2

Figure 2. Timing Diagram for AD7805/AD7809 Parallel Write

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