DSPIC30F2010 datasheet(25/236 Pages) MICROCHIP

25 / 236 page

DS70135E-page 23

dsPIC30F4011/4012

3.1.1

DATA ACCESS FROM PROGRAM

MEMORY USING TABLE

INSTRUCTIONS

This architecture fetches 24-bit wide program memory.

Consequently, instructions are always aligned. How-

ever, as the architecture is modified Harvard, data can

also be present in program space.

There are two methods by which program space can

be accessed; via special table instructions, or through

the remapping of a 16K word program space page into

the upper half of data space (see Section 3.1.2 “Data

Access From Program Memory Using Program

Space Visibility”). The TBLRDL and TBLWTL instruc-

tions offer a direct method of reading or writing the least

significant word (lsw) of any address within program

space, without going through data space. The TBLRDH

and TBLWTH instructions are the only method whereby

the upper 8 bits of a program space word can be

accessed as data.

The PC is incremented by two for each successive

24-bit program word. This allows program memory

addresses to directly map to data space addresses.

Program memory can thus be regarded as two, 16-bit

word-wide address spaces, residing side by side, each

with the same address range. TBLRDL and TBLWTL

access the space which contains the least significant

data word, and TBLRDH and TBLWTH access the space

which contains the Most Significant Byte of data.

Figure 3-2 shows how the EA is created for table oper-

ations and data space accesses (PSV = 1). Here,

P<23:0> refers to a program space word, whereas

D<15:0> refers to a data space word.

A set of table instructions is provided to move byte or

word-sized data to and from program space (see

Figure 3-3 and Figure 3-4).

TBLRDL:

Table Read Low

Word: Read the lsw of the program address;

P<15:0> maps to D<15:0>.

Byte: Read one of the LSBs of the program

address;

P<7:0> maps to the destination byte when byte

select = 0;

P<15:8> maps to the destination byte when byte

select = 1.

TBLWTL:

Table Write Low (refer to Section 6.0

“Flash Program Memory” for details on Flash

programming).

TBLRDH:

Table Read High

Word: Read the msw of the program address;

P<23:16> maps to D<7:0>; D<15:8> will always

be = 0.

Byte: Read one of the MSBs of the program

address;

P<23:16> maps to the destination byte when

byte select = 0;

The destination byte will always be ‘0’ when byte

select = 1.

TBLWTH:

Table Write High (refer to Section 6.0

“Flash Program Memory” for details on Flash

programming).

FIGURE 3-3:

PROGRAM DATA TABLE ACCESS (LEAST SIGNIFICANT WORD)

PC Address

0x000000

0x000002

0x000004

0x000006

00000000

Program Memory

‘Phantom’ Byte

(read as ‘0’).

TBLRDL.W

TBLRDL.B

(Wn<0> = 1)

TBLRDL.B

(Wn<0> = 0)

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