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HCS515 데이터시트(PDF) 8 Page - Microchip Technology |
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HCS515 데이터시트(HTML) 8 Page - Microchip Technology |
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8 / 32 page ![]() HCS515 DS40183D-page 8 © 2002 Microchip Technology Inc. 4.0 INTERFACING TO A MICROCONTROLLER The HCS515 interfaces to a microcontroller via a syn- chronous serial interface. A clock and data line are used to communicate with the HCS515. The microcon- troller controls the clock line. There are two groups of data transfer messages. The first is from the decoder whenever the decoder receives a valid transmission. The decoder signals reception of a valid code by taking the data line high (maximum of 500 ms) The microcon- troller then services the request by clocking out a data string from the decoder. The data string contains the function code, the status bit, and block indicators. The second is from the controlling microcontroller to the decoder in the form of a defined command set. Figure 4-1 shows the HCS515 decoder and the I/O interface lines necessary to interface to a microcontrol- ler. 4.1 Valid Transmission Message The decoder informs the microcontroller of a valid transmission by taking the data line high for up to 500 ms. The controlling microcontroller must acknowl- edge by taking the clock line high. The decoder then takes the data line low. The microcontroller can then begin clocking a data stream out of the HCS515. The data stream consists of: •START bit ‘0’. • 2 status bits [REPEAT, Vlow]. • 4-bit function code [S3 S2 S1 S0]. •STOP bit ‘1’. • 4 bits indicating the number of transmitters learned into the decoder [CNT3…CNT0]. • 4 bits indicating which block was used [TX3…TX0]. • 64 bits of the received transmission with the hop- ping code decrypted. Note: Data is always clocked in/out Least Significant bit (LSb) first. The decoder will terminate the transmission of the data stream at any point where the clock is kept low for longer than 1 ms. Therefore, the microcontroller can only clock out the required bits. A maximum of 80 bits can be clocked out of the decoder. FIGURE 4-1: HCS515 DECODER AND I/O INTERFACE LINES FIGURE 4-2: DECODER VALID TRANSMISSION MESSAGE NC NC VDD S1 RF DATA SYNC CLOCK SYNC DATA S0 OUTPUT HCS515 S0 MCLR NC NC NC VSS RF_IN S_CLK S_DAT NC 1 2 3 4 5 6 78 9 10 11 12 13 14 VCC X X X MICRO RESET S1 OUTPUT X X X Decoder Signal Valid TCLKH TDS AB Cii TACT TDHI TCLA Received String Ci S_DAT TX0 TX3 RX63 REPT VLOW S0 S1 S2 S3 CNT0 CNT3 0 RX0 RX1 RX62 1 S_CLK Information TACK TCLKH TCLKL Transmission |
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