PIC16 datasheet(55/418 Pages) MICROCHIP

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DS40001609C-page 55

PIC16(L)F1508/9

5.3

Clock Switching

The system clock source can be switched between

external and internal clock sources via software using

the System Clock Select (SCS) bits of the OSCCON

using the SCS bits:

• Default system oscillator determined by FOSC

bits in Configuration Words

• Secondary oscillator 32 kHz crystal

• Internal Oscillator Block (INTOSC)

5.3.1

SYSTEM CLOCK SELECT (SCS)

BITS

The System Clock Select (SCS) bits of the OSCCON

the CPU and peripherals.

• When the SCS bits of the OSCCON register = 00,

the system clock source is determined by value of

the FOSC<2:0> bits in the Configuration Words.

• When the SCS bits of the OSCCON register = 01,

the system clock source is the secondary

oscillator.

• When the SCS bits of the OSCCON register = 1x,

the system clock source is chosen by the internal

oscillator frequency selected by the IRCF<3:0>

bits of the OSCCON register. After a Reset, the

SCS bits of the OSCCON register are always

cleared.

When switching between clock sources, a delay is

required to allow the new clock to stabilize. These oscil-

lator delays are shown in Table 5-3.

5.3.2

OSCILLATOR START-UP TIMER

STATUS (OSTS) BIT

The Oscillator Start-up Timer Status (OSTS) bit in the

OSCSTAT register has different definitions that are

dependent on the FOSC bit selection in the

Configuration Word. Table 5-2 defines the OSTS bit

value for the FOSC selections.

The normal function of the OSTS bit is when

FOSC<2:0> selects one of the external oscillator

modes, HS, XT or LP, while the OST is counting pulses

on the OSC1 pin from the external oscillator,

OSTS = 0. When the OST has counted 1024 pulses,

the OSTS bit should be set, OSTS = 1, indicating the

oscillator is stable and ready to be used.

When Fail-Safe Clock Monitor and/or Two-Speed

Start-up are enabled, (FCMEN = 1 and/or IESO = 1),

the device will operate using the internal oscillator

(INTOSC) selected by the IRCF<3:0> bits, whenever

OSTS = 0.

When

the

OST

period

expires,

(OSTS = 1), the system clock will switch to the external

oscillator selected.

When Fail-Safe Clock Monitor and Two-Speed

Start-up are disabled, (FCMEN = 0 and IESO = 0), the

device will be held in Reset while OSTS = 0. When

OST period expires, (OSTS = 1), Reset will be

released and execution will begin 10 FOSC cycles later

using the external oscillator selected.

For definition of the OSTS bit with clock sources other

than external oscillator modes (HS, XT or LP), see

Table 5-2.

The OSTS bit does not reflect the status of the

secondary oscillator.

5.3.3

SECONDARY OSCILLATOR

The secondary oscillator is a separate crystal oscillator

associated with the Timer1 peripheral. It is optimized

for timekeeping operations with a 32.768 kHz crystal

connected between the SOSCO and SOSCI device

pins.

The secondary oscillator is enabled using the

T1OSCEN control bit in the T1CON register. See

Section 19.0 “Timer1 Module with Gate Control” for

more information about the Timer1 peripheral.

5.3.4

SECONDARY OSCILLATOR READY

(SOSCR) BIT

The user must ensure that the secondary oscillator is

ready to be used before it is selected as a system clock

source. The Secondary Oscillator Ready (SOSCR) bit

of the OSCSTAT register indicates whether the

secondary oscillator is ready to be used. After the

SOSCR bit is set, the SCS bits can be configured to

select the secondary oscillator.

Note:

Any automatic clock switch, which may

occur

from

Two-Speed

Start-up

Fail-Safe Clock Monitor, does not update

the SCS bits of the OSCCON register. The

user can monitor the OSTS bit of the

OSCSTAT register to determine the current

system clock source. See Table 5-2.

TABLE 5-2:

OSTS BIT DEFINITION

FOSC<2:0>

selection

SCS<1:0> bits

OSTS value

INTOSC

000

ECH, ECM, ECL,

EXTRC

100

HS, XT, LP

normal*

* Normal function for oscillator modes (OSTS = 0),

while OST counting (OSTS = 1), after OST count

has expired.

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