PIC10LF322T-EMCSQTP datasheet(47/210 Pages) MICROCHIP

47 / 210 page

 2011 Microchip Technology Inc.

Preliminary

DS41585A-page 47

PIC10(L)F320/322

6.6.2

PIE1 REGISTER

The PIE1 register contains the interrupt enable bits, as

shown in Register 6-2.

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

U-0

R/W-0/0

U-0

R/W-0/0

U-0

R/W-0/0

U-0

—ADIE

—

NCO1IE

CLC1IE

—TMR2IE

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

Unimplemented

: Read as ‘0’

bit 6

ADIE:

A/D Converter Interrupt Enable bit

= Enables the A/D converter interrupt

= Disables the A/D converter interrupt

bit 5

Unimplemented

: Read as ‘0’

bit 4

NCO1IE:

Numerically Controlled Oscillator Interrupt Enable bit

= Enables the NCO overflow interrupt

= Disables the NCO overflow interrupt

bit 3

CLC1IE:

Configurable Logic Block Interrupt Enable bit

= Enables the CLC interrupt

= Disables the CLC interrupt

bit 2

Unimplemented

: Read as ‘0’

bit 1

TMR2IE:

TMR2 to PR2 Match Interrupt Enable bit

= Enables the TMR2 to PR2 Match interrupt

= Disables the TMR2 to PR2 Match interrupt

bit 0

Unimplemented

: Read as ‘0’

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