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MP4470GL 데이터시트(PDF) 10 Page - Monolithic Power Systems

부품명 MP4470GL
상세설명  High-Efficiency, Fast-Transient, 5A, 36V Synchronous, Step-Down Converter
PDF  18 Pages
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제조업체  MPS [Monolithic Power Systems]
홈페이지  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP4470GL 데이터시트(HTML) 10 Page - Monolithic Power Systems

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MP4470/4470A–HIGH-EFFICIENCY, FAST-TRANSIENT, SYNCHRONOUS, STEP-DOWN CONVERTER
MP4470/4470A Rev. 1.1
www.MonolithicPower.com
10
8/26/2013
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
6
SW
FREQ
IN
DELAY
IN
OUT
10
F(kHz)
96 R
(k )
V
[t
(ns)]
VV
=
×Ω
+×
(3)
Where tDELAY is the comparator delay (~20ns).
The MP4470/4470A is optimized for 200kHz-to-
1MHz applications to operate at high switching
frequencies with high efficiency. The high-
switching frequency allows for smaller LC-filter
components to reduce PCB space requirements.
Ramp Compensation
Figure 4 and Figure 5 show jitter occurring in
both PWM mode and skip mode. Noise on VFB’s
downward slope causes the HS-FET ON time to
deviate from its intended position and produces
jitter. There is a relationship between system
stability and the steepness of the VFB ripple: The
slope steepness of the VFB ripple dominates
noise immunity. The magnitude of the VFB ripple
doesn’t affect the noise immunity directly.
Figure 4: Jitter in PWM Mode
Figure 3: Jitter in Skip Mode
Ceramic output capacitors lack enough ESR
ripple to stabilize the system, and requires an
external compensation ramp.
I
C4
I
FB
I
I
R4
I
FB
Figure 6: Simplified Circuit in PWM Mode with
External Ramp Compensation
In PWM mode has an equivalent circuit with HS-
FET
OFF
and
uses
a
external
ramp
compensation circuit (R4, C4), shown as a
simplified circuit in Figure 6. Derive the external
ramp from the inductor-ripple current. Choose C4,
R1, and R2 to meet the following condition:
12
SW
4
1
2
RR
11
2F
C
5
R
R
⎛⎞
×
<× ⎜⎟
π×
×
+
⎝⎠
(4)
Then:
R4
C4
FB
C4
II
I
I
=
+≈
(5)
The VFB downward slope ripple is then estimated
as:
OUT
SLOPE1
44
V
V
RC
−
=
×
(6)
From equation 6, reduce R4 or C4 to reduce
instability in PWM mode. If C4 cannot be reduced
further due to equation 4’s limitations, then only
reduce R4. Based on bench experiments, VSLOPE1
is around 20V/ms-40V/ms.
In the case of POSCAP or other types of
capacitors with higher ESR, an external ramp is
not necessary.
Figure 7: Simplified Circuit in PWM Mode without
External Ramp Compensation



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