MP5414—PMU FOR 3D GLASSES

MP5414 Rev.1.12

www.MonolithicPower.com

21

12/13/2012

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Setting the LDO Output Voltage

The LDO output voltage can be also adjusted by

using an external resistor divider (R3 and R4 in

the Functional Block Diagram). However, the

value of R3 and R4 in series should not exceed

100kΩ to minimize the impact on the internal

resistor divider. To accurately set the output

voltage, use 10kΩ (

±1%) for the low-side resistor

(R4), and determine the value of the high-side

resistor R3 using the following equation:

LDOOUT

LDOFB

LDOFB

VV

R3

R4

V

⎛⎞

−

=× ⎜⎟

⎝⎠

voltage equal to 1.222V.

For example, for a 2.5V output

2.5V 1.222V

R3

10.41k

1.222V

10k

−

==

Ω

⎛⎞

⎜⎟

Ω

⎝⎠

You can select a standard 10.5kΩ (

±1%) resistor

for R3.

The following table lists the selected standard R3

values for correlated with their output voltages:

Table 3—Adjustable LDO Output Voltage

R3 Values

R3 (Ω)

R4 (Ω)

1.25

232

1.5

2.26k

1.8

4.75k

2

6.34k

2.5

10.5k

2.8

13k

3

14.7k

3.3

16.9k

4

22.6k

5

30.9k

10k

Selecting the LDO Input Capacitor

For proper operation, place a ceramic capacitor

(C4) between 1µF and 10µF of dielectric type

X5R or X7R between the LDOIN pin and ground.

Larger values in this range will help improve line

transient response at the cost of increased size.

Selecting the LDO Output Capacitor

For stable operation, use a ceramic capacitor of

type X5R or X7R between 1µF and 10µF for the

LDOOUT capacitor, C6. Larger values in this

range will help improve load transient response

and reduce noise at the cost of increased size.

Other dielectric types can be used, but their

temperature-sensitivity can unduly influence their

capacitances.

To improve load transient response, add a small

ceramic (X5R, X7R or Y5V dielectric) 100nF

feed-forward capacitor in parallel with R3. The

feed-forward capacitor is not required for stable

operation.

Layout Considerations

Proper layout of the high frequency switching

path is critical to limit noise issues and

electromagnetic interference. The circuit loop

from BSTOUT pin, output capacitor to BSTGND

pin is flowing with high frequency pulse current. It

must be as short as possible. The BSTIN pin is

the power supply input for the internal MOSFET

switch gate driver and the internal control

circuitry and requires decoupling. For the LDO,

the input and output need bypass ceramic

capacitors close to the LDOIN pin and LDOOUT

pin respectively. Ensure all feedback connections

are short and direct. Place the feedback resistors

and compensation components as close to the

chip as possible. Connect LDOIN, LDOOUT and

especially LDOGND respectively to a large

copper area to cool the chip to improve thermal

performance and long-term reliability. See the

MP5414 demo board layout for reference.