AD7859AP datasheet(5/28 Pages) AD

5 / 28 page

AD7859/AD7859L

REV. A

–5–

ABSOLUTE MAXIMUM RATINGS

(TA = +25°C unless otherwise noted)

AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Analog Input Voltage to AGND . . . . –0.3 V to AVDD + 0.3 V

Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V

Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V

REFIN/REFOUT to AGND . . . . . . . . . –0.3 V to AVDD + 0.3 V

Input Current to Any Pin Except Supplies

2 . . . . . . . .

±10 mA

Operating Temperature Range

Commercial (A, B Versions) . . . . . . . . . . . –40

°C to +85°C

Storage Temperature Range . . . . . . . . . . . –65

°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150

°C

PQFP Package, Power Dissipation . . . . . . . . . . . . . . 450 mW

JA Thermal Impedance

. . . . . . . . . . . . . . . . . . . . . 95

°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215

°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220

°C

PLCC Package, Power Dissipation . . . . . . . . . . . . . . 500 mW

JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 55

°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215

°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220

°C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1500 kV

NOTES

1Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those listed in the

operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

2Transient currents of up to 100 mA will not cause SCR latchup.

TO OUTPUT

50pF

1.6mA

IOL

200µA

IOH

+2.1V

Figure 1. Load Circuit for Digital Output Timing

Specifications

ORDERING GUIDE

Linearity

Power

Error

Dissipation Package

Model

(LSB)

(mW)

Option

AD7859AP

±1

P-44A

AD7859AS

±1

S-44

AD7859BS

±1/2

S-44

AD7859LAS

±1

5.5

S-44

EVAL-AD7859CB

EVAL-CONTROL BOARD

NOTES

1Linearity error refers to the integral linearity error.

2P = PLCC; S = PQFP.

3L signifies the low power version.

4This can be used as a stand-alone evaluation board or in conjunction with the

EVAL-CONTROL BOARD for evaluation/demonstration purposes.

5This board is a complete unit allowing a PC to control and communicate with

all Analog Devices, Inc. evaluation boards ending in the CB designators.

For more information on Analog Devices products and evaluation boards, visit

our World Wide Web home page at http://www.analog.com.

PINOUT FOR PLCC

W/B

REFIN/REFOUT

AVDD

CREF1

AIN0

CREF2

AGND

AIN1

AIN2

AIN3

DVDD

DGND

DB5

DB6

DB7

DB8/HBEN

DB9

DB10

DB11

DB4

AD7859

(Not to Scale)

TOP VIEW

PINOUT FOR PQFP

AD7859

TOP VIEW

(Not to Scale)

PIN NO. 1 IDENTIFIER

W/B

REFIN/REFOUT

AVDD

CREF1

AIN0

CREF2

AGND

AIN1

AIN2

AIN3

DVDD

DGND

DB5

DB6

DB7

DB8/HBEN

DB9

DB10

DB11

DB4

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