AD9220ARSZ datasheet(21/32 Pages) AD

21 / 32 page

REV. E

AD9221/AD9223/AD9220

–21–

can be detected. Table V is a truth table for the over/underrange

circuit in Figure 28, which uses NAND gates. Systems requiring

programmable gain conditioning of the AD9221/AD9223/

AD9220 input signal can immediately detect an out-of-range

condition, thus eliminating gain selection iterations. Also, OTR

can be used for digital offset and gain calibration.

Table V. Out-of-Range Truth Table

OTR

MSB

Analog Input Is

In Range

Underrange

Overrange

OVER = “1”

UNDER = “1”

MSB

OTR

MSB

Figure 28. Overrange or Underrange Logic

Digital Output Driver Considerations (DVDD)

The AD9221, AD9223 and AD9220 output drivers can be

configured to interface with 5 V or 3.3 V logic families by setting

DVDD to 5 V or 3.3 V respectively. The AD9221/AD9223/

AD9220 output drivers are sized to provide sufficient output

current to drive a wide variety of logic families. However, large

drive currents tend to cause glitches on the supplies and may

affect SINAD performance. Applications requiring the AD9221/

AD9223/AD9220 to drive large capacitive loads or large fanout

may require additional decoupling capacitors on DVDD. In

extreme cases, external buffers or latches may be required.

Clock Input and Considerations

The AD9221/AD9223/AD9220 internal timing uses the two

edges of the clock input to generate a variety of internal timing

signals. The clock input must meet or exceed the minimum

specified pulsewidth high and low (tCH and tCL) specifications

for the given A/D as defined in the Switching Specifications to

meet the rated performance specifications. For example, the

clock input to the AD9220 operating at 10 MSPS may have a

duty cycle between 45% to 55% to meet this timing requirement

since the minimum specified tCH and tCL is 45 ns. For clock

rates below 10 MSPS, the duty cycle may deviate from this

range to the extent that both tCH and tCL are satisfied.

All high speed high resolution A/Ds are sensitive to the quality

of the clock input. The degradation in SNR at a given full-scale

input frequency (fIN) due to only aperture jitter (tA) can be

calculated with the following equation:

SNR

[]

1 2

log

In the equation, the rms aperture jitter, tA, represents the root-

sum square of all the jitter sources, which include the clock

input, analog input signal, and A/D aperture jitter specification.

For example, if a 5 MHz full-scale sine wave is sampled by an

A/D with a total rms jitter of 15 ps, the SNR performance of the

A/D will be limited to 66.5 dB. Undersampling applications are

particularly sensitive to jitter.

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the AD9221/

AD9223/AD9220. As such, supplies for clock drivers should be

separated from the A/D output driver supplies to avoid modulating

the clock signal with digital noise. Low jitter crystal controlled

oscillators make the best clock sources. If the clock is generated

from another type of source (by gating, dividing, or other method),

it should be retimed by the original clock at the last step.

Most of the power dissipated by the AD9221/AD9223/AD9220

is from the analog power supplies. However, lower clock speeds

will reduce digital current slightly. Figure 29 shows the relation-

ship between power and clock rate for each A/D.

CLOCK FREQUENCY – MHz

3.0

2.5

5V p-p

2V p-p

2.0

1.5

1.0

0.5

Figure 29a. AD9221 Power Consumption vs. Clock

Frequency

CLOCK FREQUENCY – MHz

125

120

105

115

110

5V p-p

2V p-p

100

Figure 29b. AD9223 Power Consumption vs. Clock

Frequency

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