PIC24HJ128GP310 datasheet(17/286 Pages) MICROCHIP

17 / 286 page

DS70175F-page 15

PIC24HJXXXGPX06/X08/X10

2.0

CPU

The PIC24HJXXXGPX06/X08/X10 CPU module has a

16-bit (data) modified Harvard architecture with an

enhanced instruction set and addressing modes. The

CPU has a 24-bit instruction word with a variable length

opcode field. The Program Counter (PC) is 23 bits wide

and addresses up to 4M x 24 bits of user program

memory space. The actual amount of program memory

implemented varies by device. A single-cycle instruction

prefetch mechanism is used to help maintain throughput

and provides predictable execution. All instructions

execute in a single cycle, with the exception of

instructions that change the program flow, the double

word move (MOV.D) instruction and the table instructions.

Overhead-free, single-cycle program loop constructs are

supported using the REPEAT instruction, which is

interruptible at any point.

The

PIC24HJXXXGPX06/X08/X10

devices

have

sixteen, 16-bit working registers in the programmer’s

model. Each of the working registers can serve as a data,

address or address offset register. The 16th working

for interrupts and calls.

The PIC24HJXXXGPX06/X08/X10 instruction set

includes many addressing modes and is designed for

optimum C compiler efficiency. For most instructions,

the PIC24HJXXXGPX06/X08/X10 is capable of

executing a data (or program data) memory read, a

working register (data) read, a data memory write and

a program (instruction) memory read per instruction

cycle. As a result, three parameter instructions can be

supported, allowing A + B = C operations to be

executed in a single cycle.

A block diagram of the CPU is shown in Figure 2-1,

and

the

programmer’s

model

for

the

PIC24HJXXXGPX06/X08/X10 is shown in Figure 2-2.

2.1

Data Addressing Overview

The data space can be linearly addressed as 32K words

or 64 Kbytes using an Address Generation Unit (AGU).

The upper 32 Kbytes of the data space memory map can

optionally be mapped into program space at any 16K

program word boundary defined by the 8-bit Program

Space Visibility Page (PSVPAG) register. The program

to data space mapping feature lets any instruction

access program space as if it were data space.

The data space also includes 2 Kbytes of DMA RAM,

which is primarily used for DMA data transfers, but may

be used as general purpose RAM.

2.2

Special MCU Features

The PIC24HJXXXGPX06/X08/X10 features a 17-bit by

17-bit, single-cycle multiplier. The multiplier can

perform

signed,

unsigned

and

mixed-sign

multiplication. Using a 17-bit by 17-bit multiplier for

16-bit by 16-bit multiplication makes mixed-sign

multiplication possible.

The PIC24HJXXXGPX06/X08/X10 supports 16/16 and

32/16 integer divide operations. All divide instructions

are iterative operations. They must be executed within

a REPEAT loop, resulting in a total execution time of 19

instruction cycles. The divide operation can be

interrupted during any of those 19 cycles without loss

of data.

A multi-bit data shifter is used to perform up to a 16-bit,

left or right shift in a single cycle.

Note:

This data sheet summarizes the features

this

group

of PIC24HJXXXGPX06/X08/X10 devices.

It is not intended to be a comprehensive

reference source. To complement the

information in this data sheet, refer to the

“PIC24H Family Reference Manual”.

Refer

the

Microchip

web

site

(www.microchip.com)

for

the

latest

PIC24H

Family

Reference

Manual

sections.

PIC24HJ128GP310 데이터시트(PDF) 17 Page - Microchip Technology

PIC24HJ128GP310 데이터시트(HTML) 17 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL