REV. B

AD7722

–9–

PIN CONFIGURATION

44-Lead MQFP (S-44B)

3

4

5

6

7

1

2

10

11

8

9

40 39 38

41

42

43

44

36 35 34

37

29

30

31

32

33

27

28

25

26

23

24

PIN 1

IDENTIFIER

TOP VIEW

(Not to Scale)

12 13 14 15 16 17 18 19 20 21 22

AD7722

DGND/DB13

DGND/DB14

DGND/DB15

SYNC

CS

DGND

CAL

AGND

AGND

REF2

DGND/DB2

DGND/DB1

DGND/DB0

CFMT/

DRDY

DVAL/

RD

DGND

UNI

P/

S

AGND

AGND1

CLKIN

PARALLEL MODE PIN FUNCTION DESCRIPTIONS

Mnemonic

Pin No. Description

DVAL/

RD

5

Read input is a level sensitive logic input. The

RD logic level is sensed on the rising edge of CLKIN. This

digital input can be used in conjunction with

CS to read data from the device. The output data bus is

enabled when the rising edge of CLKIN senses a logic low level on

RD if CS is also low. When RD is

sensed high, the output data bits DB15–DB0 will be high impedance.

CFMT/

DRDY

4Data Ready Logic Output. A falling edge indicates a new output word is available to be read from the

output data register.

DRDY will return high upon completion of a read operation. If a read operation does

not occur between output updates,

DRDY will pulse high for two CLKIN cycles before the next output

update.

DRDY also indicates when conversion results are available after a SYNC or RESET sequence

and when completing a self-calibration.

DGND/DB15

31

Data Output Bit (MSB).

DGND/DB14

32

Data Output Bit.

DGND/DB13

33

Data Output Bit.

DGND/DB12

34

Data Output Bit.

DGND/DB11

35

Data Output Bit.

DGND/DB10

36

Data Output Bit.

FSO/DB9

37

Data Output Bit.

SDO/DB8

38

Data Output Bit.

SCO/DB7

40

Data Output Bit.

FSI/DB6

41

Data Output Bit.

SFMT/DB5

42

Data Output Bit.

DOE/DB4

43

Data Output Bit.

TSI/DB3

44

Data Output Bit.

DGND/DB2

1

Data Output Bit.

DGND/DB1

2

Data Output Bit.

DGND/DB0

3

Data Output Bit (LSB).