Am29DL800B

33

P R E L I M I NARY

AC CHARACTERISTICS

OE#

CE#

WE#

Addresses

Data

Valid

In

Valid

In

Valid PA

Valid RA

Valid

Out

Valid

In

CE# Controlled Write Cycles

WE# Controlled Write Cycle

Valid PA

Valid PA

Read Cycle

21519A-23

Figure 19.

Back-to-Back Read/Write Cycle Timings

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

21519A-24

Figure 20.

Data# Polling Timings (During Embedded Algorithms)

WE#

CE#

OE#

High Z

High Z

DQ7

DQ0–DQ6

RY/BY#

Complement

True

Addresses

VA

VA

VA

Status Data

Complement

Status Data

True

Valid Data

Valid Data