AM79C960KCW datasheet(27/127 Pages) AMD

27 / 127 page

P R E L I M I N A R Y

AMD

1-369

Am79C960

PRDB0-7

Private Data Bus

Input/Output

This is the data bus for the static RAM, the Boot PROM,

and the Address PROM.

SLEEP

Sleep

Input

When

SLEEP input is asserted (active LOW), the

PCnet-ISA controller performs an internal system reset

and proceeds into a power savings mode. All outputs

will be placed in their normal reset condition. All PCnet-

ISA controller inputs will be ignored except for the

SLEEP pin itself. Deassertion of SLEEP results in

wake-up. The system must delay the starting of the net-

work controller by 0.5 seconds to allow internal analog

circuits to stabilize.

SMA

Shared Memory Architecture

Input

This pin is sampled after the hardware RESET se-

quence. The pin must be pulled permanently LOW for

operation in the shared memory mode.

SMAM

Shared Memory Address Match

Input

This pin indicates an access to shared memory when

active. The type of access is decided by

MEMR or

MEMW.

SROE

Static RAM Output Enable

Output

This pin directly controls the external SRAM’s

OE pin.

SRWE

Static RAM Write Enable

Output

This pin directly controls the external SRAM’s

WE pin.

Test Enable

Input

This pin is for factory use only. It has a default value of

HIGH if left unconnected. It is strongly recommended

that this pin always be connected to VDD.

XTAL1

Crystal Connection

Input

The internal clock generator uses a 20 MHz crystal that

is attached to pins XTAL1 and XTAL2. Alternatively, an

external 20 MHz CMOS-compatible clock signal can be

used to drive this pin. Refer to the section on External

Crystal Characteristics for more details.

XTAL2

Crystal Connection

Output

The internal clock generator uses a 20 MHz crystal that

is attached to pins XTAL1 and XTAL2. If an external

clock is used, this pin should be left unconnected.

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