AM79C981 datasheet(20/40 Pages) AMD

20 / 40 page

AMD

PRELIMINARY

1–90

Am79C981

IMR+ Chip

XTAL

OSC

ASYNC

RESET

RST

STR

CLR

1/2 ’74

TCK

SIPO

1/2 ’74

TCK

SCLK

17306B-7

TEST

Figure 3. Minimum Mode, Non-Intelligent Repeater Example

CRS

(Note 2)

STR

CRS

AUI

CRS

TP0

CRS

TP1

CRS

TP2

CRS

TP3

CRS

TP4

CRS

TP5

CRS

TP6

CRS

TP7

CRS

AUI

TCK

(Note 1)

(Note 3)

AUI

TP0

TP1

TP2

TP3

TP4

TP5

TP6

TP7

AUI

17306B-8

Notes:

1. Externally generated signal illustrates internal IMR+ chip clock phase relationship.

2. CRS timing with the C-bit cleared (IMR+ Chip Programmable Options)

3. For Minimum Hub Mode

Figure 4. Management Port Minimum Mode and

Port Activity Monitor Signal Relationship

Port Activity Monitor

Two pins, CRS and STR, are used to serially output the

state of the internal Carrier Sense signals from the AUI

and the eight TP ports. This function together with exter-

nal hardware and/or software can be used to monitor re-

peater receive and/or collision activity.

The following diagram shows typical external hardware

employed to convert the serial bit stream into parallel

form. The accuracy of the CRS signals is 10 Bit Times

(BT) (1

µs). Specifically, a transition to active state by

any of the internal carrier sense bits that lasts for less

than 10BT is latched internally and is used to set the ap-

propriate bit during the next sample period.

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