AM79C985 datasheet(38/48 Pages) AMD

38 / 48 page

Am79C985

PRELIMINARY

SWITCHING CHARACTERISTICS (continued)

Notes:

1. Parameter not tested.

2. DI pulses narrower than tPWODI (min) will be rejected; pulses wider than tPWODI (max) will turn internal DI carrier sense on.

3. DI pulses narrower than tPWKDI (min) will maintain internal DI carrier on; pulses wider than tPWKDI (max) will turn internal DI

carrier sense off.

4. CI pulses narrower than tPWOCI (min) will be rejected; pulses wider than tPWOCI (max) will turn internal CI carrier sense on.

5. CI pulses narrower than tPWKCI (min) will maintain internal CI carrier on; pulses wider than tPWKCI (max) will turn internal CI

carrier sense off.

6. RXD pulses narrower than tPWKRD (min) will maintain internal RXD carrier sense on; a pulse wider than tPWKRD (max) will

turn RXD carrier sense off.

Parameter

Symbol

Parameter Description

Test Conditions

Min

Max

Unit

Twisted Pair Port Timing

tTXTD

CLK Rising Edge to TXD

± Transition Delay

–

tTETD

Transmit End of Transmission

250

375

tPWKRD

RXD Pulse Width Maintain/Turn-off

Threshold

|VIN|>|VTHS| (Note 6)

136

200

tPERLP

Idle Signal Period

tPWLP

Idle Link Test Pulse Width

120

Management Port Timing

tSCLK

SCLK Clock Period

100

–

tSCLKH

SCLK Clock HIGH

–

tSCLKL

SCLK Clock LOW

–

tSCLKR

SCLK Clock Rise Time

–

tSCLKF

SCLK Clock Fall Time

–

tSISET

SI Input Setup Time to SCLK Rising Edge

–

tSIHLD

SI Input Hold Time from SCLK Rising Edge

–

tSODLY

SO Output Delay from SCLK Rising Edge

CL = 100 pF

–

tCLKHCRS

CLK Rising Edge to CRS valid

CL = 100 pF

tSTRSET

STR Setup Time

–

tSTRHLD

STR Hold Time

–

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