CD00237391 datasheet(128/177 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F20xxx

128/177

Doc ID 15818 Rev 9

Synchronous waveforms and timings

Figure 58 through Figure 61 represent synchronous waveforms and Table 75 through

Table 77 provide the corresponding timings. The results shown in these tables are obtained

with the following FSMC configuration:

●

BurstAccessMode = FSMC_BurstAccessMode_Enable;

●

MemoryType = FSMC_MemoryType_CRAM;

●

WriteBurst = FSMC_WriteBurst_Enable;

●

CLKDivision = 1; (0 is not supported, see the STM32F20xxx/21xxx reference manual)

●

DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM

In all timing tables, the THCLK is the HCLK clock period.

Figure 58.

Synchronous multiplexed NOR/PSRAM read timings

FSMC_CLK

FSMC_NEx

FSMC_NADV

FSMC_A[25:16]

FSMC_NOE

FSMC_AD[15:0]

AD[15:0]

FSMC_NWAIT

(WAITCFG = 1b, WAITPOL + 0b)

FSMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b)

tw(CLK)

Data latency = 0

BUSTURN = 0

td(CLKL-NExL)

td(CLKL-NExH)

td(CLKL-NADVL)

td(CLKL-AV)

td(CLKL-NADVH)

td(CLKL-AIV)

td(CLKH-NOEL)

td(CLKL-NOEH)

td(CLKL-ADV)

td(CLKL-ADIV)

tsu(ADV-CLKH)

th(CLKH-ADV)

tsu(ADV-CLKH)

th(CLKH-ADV)

tsu(NWAITV-CLKH)

th(CLKH-NWAITV)

tsu(NWAITV-CLKH)

th(CLKH-NWAITV)

tsu(NWAITV-CLKH)

th(CLKH-NWAITV)

ai14893h

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