STM32F101ZC datasheet(97/112 Pages) STMICROELECTRONICS

97 / 112 page

STM32F101xC, STM32F101xD, STM32F101xE

Electrical characteristics

Doc ID 14610 Rev 8

97/112

Figure 52.

Power supply and reference decoupling (VREF+ connected to VDDA)

VREF+ and VREF- inputs are available only on 100-pin packages.

5.3.19

DAC electrical specifications

VREF+/VDDA

STM32F10xxx

1 µF // 10 nF

VREF–/VSSA

ai14381b

Table 59.

DAC characteristics

Symbol

Parameter

Min

Typ

Max(1)

Unit

Comments

VDDA

Analog supply voltage

2.4

3.6

VREF+

Reference supply voltage

2.4

3.6

VREF+ must always be below

VDDA

VSSA

Ground

RLOAD

(2)

Resistive load with buffer ON

(2)

Impedance output with buffer

OFF

When the buffer is OFF, the

minimum resistive load

between DAC_OUT and VSS to

have a 1% accuracy is 1.5 M

CLOAD

(2)

Capacitive load

Maximum capacitive load at

DAC_OUT pin (when the buffer

is ON).

DAC_OUT

min(2)

Lower DAC_OUT voltage with

buffer ON

0.2

It gives the maximum output

excursion of the DAC.

It corresponds to 12-bit input

code (0x0E0) to (0xF1C) at

VREF+ = 3.6 V and (0x155) and

(0xEAB) at VREF+ = 2.4 V.

DAC_OUT

max(2)

Higher DAC_OUT voltage with

buffer ON

VDDA – 0.2

DAC_OUT

min(2)

Lower DAC_OUT voltage with

buffer OFF

0.5

It gives the maximum output

excursion of the DAC.

DAC_OUT

max(2)

Higher DAC_OUT voltage with

buffer OFF

VREF+ – 1LSB V

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